ADS825 datasheet(2/12 Pages) BURR-BROWN

Part #	ADS825

Description	10-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTERS

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Manufacturer	BURR-BROWN [Burr-Brown (TI)]

Direct Link	http://www.burr-brown.com

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2 / 12 page

2

®

ADS822, ADS825

SPECIFICATIONS

At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.

CMOS-Compatible

Rising Edge of Convert Clock

CMOS-Compatible

Straight Offset Binary

CMOS-Compatible

Straight Offset Binary

ADS822E

ADS825E(1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

RESOLUTION

10 Guaranteed

Bits

SPECIFIED TEMPERATURE RANGE

Ambient Air

–40 to +85

°C

ANALOG INPUT

Standard Single-Ended Input Range

2Vp-p

1.5

3.5

TT

V

Optional Single-Ended Input Range

1Vp-p

2

3

TT

V

Common-Mode Range

2.5

T

V

Optional Differential Input Range

2Vp-p

2

3

TT

V

Analog Input Bias Current

1

T

µA

Input Impedance

1.25 || 5

T

M

Ω || pF

Track-Mode Input Bandwidth

–3dBFS Input

300

T

MHz

CONVERSION CHARACTERISTICS

Sample Rate

10k

40M

TT

Samples/s

Data Latency

5

T

Clk Cyc

DYNAMIC CHARACTERISTICS

Differential Linearity Error (largest code error)

f = 1MHz

±0.25

±1.0

TT

LSB

f = 10MHz

±0.5

T

LSB

No Missing Codes

Guaranteed

Integral Nonlinearity Error, f = 1MHz

±0.5

±2.0

TT

LSBs

Spurious Free Dynamic Range(2)

Referred to Full Scale

f = 1MHz

72

71

dBFS(3)

f = 10MHz

63

66

60

65

dBFS

Two-Tone Intermodulation Distortion(4)

f = 9.5MHz and 9.9MHz (–7dB each tone)

–67

T

dBc

Signal-to-Noise Ratio (SNR)

Referred to Full Scale

f = 1MHz

60

T

dB

f = 10MHz

57

60

TT

dB

Signal-to-(Noise + Distortion) (SINAD)

Referred to Full Scale

f = 1MHz

59

T

dB

f = 10MHz

56

58

TT

dB

Effective Number of Bits(5), f = 1MHz

9.5

T

Bits

Output Noise

Input Tied to Common-Mode

0.2

T

LSBs rms

Aperture Delay Time

3

T

ns

Aperture Jitter

1.2

T

ps rms

Overvoltage Recovery Time

2

T

ns

Full-Scale Step Acquisition Time

5

T

ns

DIGITAL INPUTS

Logic Family

Convert Command

Start Conversion

High Level Input Current(6) (VIN = 5VDD)

100

T

µA

Low Level Input Current (VIN = 0V)

10

T

µA

High Level Input Voltage

+3.5

+2.0

V

Low Level Input Voltage

+1.0

+0.8

V

Input Capacitance

5

T

pF

DIGITAL OUTPUTS

Logic Family

Logic Coding

Low Output Voltage (IOL = 50µA to 1.6mA)

VDRV = 5V

+0.1

T

V

High Output Voltage, (IOH = 50µA to 0.5mA)

+4.9

T

V

Low Output Voltage, (IOL = 50µA to 1.6mA)

VDRV = 3V

+0.1

T

V

High Output Voltage, (IOH = 50µA to 0.5mA)

+2.8

T

V

3-State Enable Time

OE = H to L

2

40

TT

ns

3-State Disable Time

OE = L to H

2

10

TT

ns

Output Capacitance

5

T

pF

ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted)

Zero Error (referred to –FS)

at 25

°C

±1.0

±3.0

TT

% FS

Zero Error Drift (referred to –FS)

5

T

ppm/

°C

Midscale Offset Error

at 25

°C

±0.29

% FS

Gain Error(7)

at 25

°C

±1.5

±2.5

TT

% FS

Gain Error Drift(7)

38

T

ppm/

°C

Gain Error(8)

at 25

°C

±0.75

±1.5

TT

% FS

Gain Error Drift(8)

25

T

ppm/

°C

Power Supply Rejection of Gain

∆ V

S = ±5%

70

T

dB

REFT Tolerance

Deviation From Ideal 3.5V

±10

±25

TT

mV

REFB Tolerance

Deviation From Ideal 1.5V

±10

±25

TT

mV

External REFT Voltage Range

REFB + 0.8

3.5

VS – 1.25

TT

T

V

External REFB Voltage Range

1.25

1.5

REFT – 0.8

TT

T

V

Reference Input Resistance

REFT to REFB

1.6

T

k

Ω

TTL, +3V/+5V CMOS-Compatible

Rising Edge of Convert Clock

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