7

ADS831

®

APPLICATION INFORMATION

THEORY OF OPERATION

The ADS831 is a high-speed CMOS analog-to-digital con-

verter which employs a pipelined converter architecture

consisting of 6 internal stages. Each stage feeds its data into

the digital error correction logic ensuring excellent differen-

tial linearity and no missing codes at the 8-bit level. The

output data becomes valid on the rising clock edge (see

Timing Diagram). The pipeline architecture results in a data

latency of 4 clock cycles.

The analog input of the ADS831 is a differential track and

hold, see Figure 1. The differential topology along with

tightly matched capacitors produce a high level of ac perfor-

mance while sampling at very high rates.

The ADS831 allows its analog inputs to be driven either

single-ended or differentially. The typical configuration for

the ADS831 is for the single-ended mode in which the input

track and hold performs a single-ended to differential con-

version of the analog input signal.

Both inputs (IN, IN) require external biasing using a com-

mon-mode voltage that is typically at the mid-supply level

The following application discussion focuses on the single-

ended configuration. Typically, its implementation is easier

to achieve and the rated specifications for the ADS831 are

characterized using the single-ended mode of operation.

DRIVING THE ANALOG INPUT

The ADS831 achieves excellent ac performance either in the

single-ended or differential mode of operation. The selection

for the optimum interface configuration will depend on the

individual application requirements and system structure.

For example, communication applications often process a

band of frequencies that does not include DC, whereas in

imaging applications, the previously restored DC level must

be maintained correctly up to the A/D converter. Features on

the ADS831, such as the input range select (RSEL pin) or

the option for an external reference, provide the needed

flexibility to accommodate a wide range of applications. In

any case, the ADS831 should be configured such that the

application objectives are met while observing the headroom

requirements of the driving amplifier in order to yield the

best overall performance.

INPUT CONFIGURATIONS

AC-Coupled, Single-Supply Interface

Figure 2 shows the typical circuit for an ac-coupled analog

input configuration of the ADS831 where all components

are powered from a single +5V supply.

With the RSEL pin connected HIGH, the full scale input

range is set to 2Vp-p. In this configuration, the top and

bottom references (REFT, REFB) provide an output voltage

of +3.0V and +2.0V, respectively. Two resistors ( 2 x 1k

Ω)

proximately +2.5V to bias the inputs of the driving ampli-

fier. Using the OPA681 on a single +5V supply, its ideal

common-mode point is +2.5V. This coincides with the

recommended common-mode input level for the ADS831

thus, obviating the need for a coupling capacitor between the

amplifier and the converter. Even though the OPA681 has an

ac gain of +2, the dc gain is only +1 due to the blocking

output of the op amp and the input of the ADS831 will be

beneficial in almost all interface configurations. This will

de-couple the op amp’s output from the capacitive load and

avoid gain peaking, which can result in increased noise. For

best spurious and distortion performance, the resistor value

should be kept below 75

Ω. The series resistor in combina-

tion with the 47pF capacitor establishes a passive low-pass

filter limiting the bandwidth for the wideband noise thus

help improving the SNR performance.

AC-Coupled, Dual Supply Interface

The circuit provided in Figure 3 shows typical connections

for the analog input in case the selected amplifier operates

on dual supplies. This might be necessary to take full

advantage of very low distortion operational amplifiers, like

the OPA642. The advantage is that the driving amplifier can

be operated with a ground referenced bipolar signal swing.

This will keep the distortion performance at its lowest since

the signal range stays within the linear region of the op amp

and sufficient headroom to the supply rails can be main-

tained. By capacitively coupling the single-ended signal to

the input of the ADS831, its common-mode requirements

can easily be satisfied with two resistors connected between

the top and bottom reference.

FIGURE 1. Simplified Circuit of Input Track and Hold with

Timing Diagram.

φ1

φ1

φ2

φ1

φ1

φ1

φ1

φ1

φ2

φ1

φ2

φ1

φ2

IN

IN

OUT

OUT

Op Amp

Bias

V

CM

Op Amp

Bias

V

CM

C

H

C

I

C

I

C

H

Input Clock (50%)

Internal Non-overlapping Clock