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DAC707KP-3 Datasheet(PDF) 8 Page - Burr-Brown (TI) |
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DAC707KP-3 Datasheet(HTML) 8 Page - Burr-Brown (TI) |
8 / 11 page ® DAC707/708/709 8 VOLTAGE OUTPUT MODELS Analog Output Analog Output Unipolar, 0 to +10V(1) Bipolar, ±10V Bipolar, ±5V 16-Bit 15-Bit 14-Bit Units 16-Bit 15-Bit 14-Bit 16-Bit 15-Bit 14-Bit Units One LSB 153 305 610 µV One LSB 305 610 1224 153 305 610 µV FFFFH +9.99985 +9.99969 +9.99939 V 7FFFH +9.99960 +9.99939 +9.99878 +4.99980 +4.99970 +4.99939 V 0000H 0 0 0 V 8000H –10.0000 –10.0000 –10.0000 –5.0000 –5.0000 –5.0000 V CURRENT OUTPUT MODELS Analog Output Analog Output Unipolar, 0 to –2mA(1) Bipolar, ±1mA 16-Bit 15-Bit 14-Bit Units 16-Bit 15-Bit 14-Bit Units One LSB 0.031 0.061 0.122 µA One LSB 0.031 0.061 0.122 µA FFFFH –1.99997 –1.99994 –1.99988 mA 7FFFH –0.99997 –0.99994 –0.99988 mA 0000H 0 0 0 mA 8000H +1.00000 +1.00000 +1.00000 mA Digital Input Code Digital Input Code Digital Input Code Digital Input Code TABLE II. Digital Input and Analog Output Voltage/Current Relationships. NOTE: (1) MSB assumed to be inverted externally. INTERFACE LOGIC AND TIMING DAC708/709 The signals CHIP SELECT (CS), WRITE (WR), register enables (A 0, A1, and A2) and CLEAR (CLR), provide the control functions for the microprocessor interface. They are all active in the “low” or logic “0” state. CS must be low to access any of the registers. A 0 and A1 steer the input 8-bit data byte to the low- or high-byte input latch respectively. A 2 gates the contents of the two input latches through to the D/A latch in parallel. The contents are then applied to the input of the D/A converter. When WR goes low, data is strobed into the latch or latches which have been enabled. The serial input mode is activated when both A 0 and A1 are logic “0” simultaneously. The D0 (D8)/SI input data line accepts the serial data MSB first. Each bit is clocked in by a WR pulse. Data is strobed through to the D/A latch by A 2 going to logic “0” the same as in the parallel input mode. Each of the latches can be made “transparent” by maintain- ing its enable signal at logic “0”. However, as stated above, when both A 0 and A 1 are logic “0” at the same time, the serial mode is selected. The CLR line resets both input latches to all zeros and sets the D/A latch to 0000 H. This is the binary code that gives a null, or zero, at the output of the D/A in the bipolar mode. In the unipolar mode, activating CLR will cause the output to go to one-half of full scale. The maximum clock rate of the latches is 10MHz. The minimum time between write (WR) pulses for successive enables is 20ns. In the serial input mode (DAC708 and DAC709), the maximum rate at which data can be clocked into the input shift register is 10MHz. The timing of the control signals is given in Figure 6. DAC707 The DAC707 interface timing is the same as that described above except instead of two 8-bit separately-enabled input latches, it has a single 16-bit input latch enabled by A 0. The TIMING DIAGRAM D0-D15, SI WR CS t CW t DW A 0, A1, A2 t AW t DH t WP LOGIC TIMING - Parallel or Serial Data Input Over Temperature ns, min ns, max TDW Data valid to end of WR 80 TCW CS valid to end of WR 80 TAW A0, A1, A2 valid to end of WR 80 TWP Write pulse width 80 TDH Data hold after end of WR 0 FIGURE 6. Logic Timing Diagram. D/A latch is enabled by A 1 . Also, there is no serial-input mode and no CHIP SELECT (CS) line. INSTALLATION CONSIDERATIONS Due to the extremely-high accuracy of the D/A converter, system design problems such as grounding and contact resistance become very important. For a 16-bit converter with a +10V full-scale range, 1LSB is 153 µV. With a load current of 5mA, series wiring and connector resistance of only 30m Ω will cause the output to be in error by 1LSB. To understand what this means in terms of a system layout, the resistance of typical 1 ounce copper-clad printed circuit board material is approximately 1/2m Ω per square. In the example above, a 10 milliinch-wide conductor 60 milliinches long would cause a 1LSB error. |
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