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DDC101U Datasheet(PDF) 7 Page - Burr-Brown (TI) |
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DDC101U Datasheet(HTML) 7 Page - Burr-Brown (TI) |
7 / 27 page 7 DDC101 ® PIN DESCRIPTIONS (CONT) PIN NUMBER NAME DESCRIPTION 18 DATA TRANSMIT In This input controls the transmission of data from the serial I/O register of the DDC101. It can be activated anytime after DATA VALID out becomes active. It must remain active until all data has been collected from the serial I/O register(s) of all DDC101s in the data path. 19 READ DATA/ This input can be used to read back the current SETUP data. When this input is held high, the output from DATA SETUP In OUTPUT is the data collected by the DDC101. When this input is pulled low, an internal shift register is loaded with the current SETUP data on the rising edge of DATA CLOCK. This SETUP data shift register is logically connected between DATA INPUT and DATA OUTPUT pins and can be read in the same way that the data output is read. SETUP data read back does not invalidate data already stored in the DDC101's serial I/O register or data being collected by the DDC101, although digital noise concerns should be considered as discussed in DATA CLOCK. 20 SETUP In This input pin controls the DDC101 SETUP. A 12-bit digital word transmitted into this pin controls Acquisition Time, K, Oversampling, M, Multiple Integrations, L, Input Range and Output Data Format. The DDC101 reads the SETUP code at this pin after the RESET SETUP input transitions from active to inactive. The SETUP code is read into the SETUP register on the 12 positive data clock transitions following that transition. 21 RESET SETUP Resets SETUP register only, does not reset balance of DDC101. The DDC101 reads SETUP input data after this input transitions from active (reset) to inactive. 22 TEST In This is a digital input that controls the connection of an internal DC current source to the DDC101's input. TEST In exercises the DDC101 and is intended to test for functionality only. The typical test input current is 100nA ±20nA. The quiescent current of the DDC101 increases by approximately 1mA when TEST In is active. When TEST is HIGH, the internal current source is ON and current is flowing into the DDC101 input. When TEST is LOW, the current source is disconnected from the input. 23 V REF An external –2.5V reference must be connected to the REFERENCE In pin. Use of an external reference allows multiple DDC101s to use the same system reference for optimum channel matching. The external reference should be filtered to minimize noise contribution (see Figure 24). 24 REFERENCE An external capacitor of 10 µF should be connected to this node to provide proper operation of the internal BUFFER BYPASS D/A converter. The REFERENCE In pin is connected to an internal reference buffer amplifier. The internal reference buffer drives the internal CDAC. This buffer output is not intended for external use. SECTION 4 TIMING CHARACTERISTICS All specifications with Unipolar input range, TINT = 1ms, Current Input, Correlated Double Sampling enabled, Sys Clock = 2MHz, VREF = –2.5V, TA = +25°C and VS = ±5VDC, unless otherwise noted. SYMBOL DESCRIPTION MIN TYP MAX UNITS t1 FDS Setup 30 ns t2 FDS width, Continuous Conversion 50 (M–1) Clocks+t1+100ns ns t3 FDS width, Asynchronous Conversion M Clocks+t1 ns t4 FDS HIGH to start of next integration, Asynchronous Conversion 50 ns t5 Setup time for RESET SETUP HIGH to DATA CLOCK HIGH 60 ns t6 Setup time for Setup Codes data valid before rising edge of DATA Clock 30 ns t7 Hold time for Setup Codes data valid after rising edge of DATA Clock 30 ns t8 Propagation delay from rising edge of SYSTEM CLOCK to DATA VALID LOW 50 ns t9 Propagation delay from DATA TRANSMIT LOW to DATA VALID HIGH 35 ns t10 Setup time for DATA CLOCK LOW to DATA TRANSMIT LOW 30 ns t11 Propagation delay from DATA TRANSMIT LOW to valid data out 30 ns t12 Hold time that Data output is valid after falling edge of DATA CLOCK 10 ns t13 Propagation delay from DATA TRANSMIT HIGH to Data Output tri-stated 40 ns t14 Propagation delay from falling edge of SYSTEM CLOCK to OVERFLOW+ and 25 ns OVERFLOW–cleared t15 SYSTEM CLOCK pulse width HIGH 240 ns t16 SYSTEM CLOCK pulse width LOW 240 ns t17 DATA VALID LOW to DATA TRANSMIT LOW, Single DDC101 30 (LxN–21) Clocks ns |
Similar Part No. - DDC101U |
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Similar Description - DDC101U |
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