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96SMF406A30 Datasheet(PDF) 1 Page - Wolfgang Knap |
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96SMF406A30 Datasheet(HTML) 1 Page - Wolfgang Knap |
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1 / 1 page Ceramic Ceramic Glass Tungsten (metalized) Gold / Nickel (surface) / (under) Compliant Lid Base Sealing Terminal Terminal plating RoHS 91SMOP 91SMOP Package Item Package Item 82 Crystal Clock Oscillators TF T t 90% or 80% VDD 10% or 20% VDD OV DC Symmetry=t/T×100(%) 50% VDD TR GND VOH ("1"Level) VOL ("0"Level) VDD 7.0 ±0.2 1.4 1.4 3.68 5.08 #3 #4 #2 #1 #2 #1 #3 #4 PIN 1 CONNECTION "L" 2 GND 3Z OPEN or "H" OUTPUT Z : high impedance 4VDD 91SMOP OUTPUT WAVEFORM V DC Power Supply CL : including fixture and probe capacitance. VDD VDD CL Test Point #2 #3 OUTPUT TRI-STATE GND #1 #4 A TEST CIRCUIT 1.8 3.28 1.8 5.08 0.01μF ∼ 0.1μF SOLDERING PATTERN 91SMOP 91SMOP (+3.0V, +3.3V or +5V PROGRAMMABLE MODELS) STANDARD SMD CLOCK OSCILLATORS STANDARD SPECIFICATIONS Item Specifications STANDARD SPECIFICATIONS PACKAGE DATA 91SMOP※1 1.000 MHz to 200.000 MHz 1.000 MHz to 80.000 MHz 91SMOP(A) : ±100 ppm 91SMOP(J) : ±100 ppm 91SMOP(B) : ±50 ppm 91SMOP(K) : ±50 ppm -20˚C to +75˚C +3.0V ±10%, +3.3V ±10% or +5V ±10% +3.0V & +3.3V models SMI P/N +3.0V & +3.3V models SMI P/N VIH : +2.2 VDD min. 91SMOP(3VA)OE VIH : +2.2 VDD min. 91SMOP(3VJ)OE VIL : +0.5 VDD max. 91SMOP(3VB)OE VIL : +0.5 VDD max. 91SMOP(3VK)OE +5V models SMI P/N +5V models SMI P/N VIH : +4.0 VDD min. 91SMOP(5VA)OE VIH : +4.0 VDD min. 91SMOP(5VJ)OE VIL : +0.5 VDD max. 91SMOP(5VB)OE VIL : +0.5 VDD max. 91SMOP(5VK)OE +3.0V & +3.3V models SMI P/N +3.0V & +3.3V models SMI P/N VIH : +2.2 VDD min. 91SMOP(3VA)SB VIH : +2.2 VDD min. 91SMOP(3VJ)SB VIL : +0.5 VDD max. 91SMOP(3VB)SB VIL : +0.5 VDD max. 91SMOP(3VK)SB +5V models SMI P/N +5V models SMI P/N VIH : +4.0 VDD min. 91SMOP(5VA)SB VIH : +4.0 VDD min. 91SMOP(5VJ)SB VIL : +0.5 VDD max. 91SMOP(5VB)SB VIL : +0.5 VDD max. 91SMOP(5VK)SB -0.5V to +7.0V DC -55˚C to +125˚C 30 mA max. 20 mA max. 30 mA max. 20 mA max. 50 mA max. 30 mA max. 50μA max. (VDD = +3.0V & Pin #1=VIL) 45% to 55% at 50%VDD level (1.00MHz to 80.00MHz) 40% to 60% at 50%VDD level (80.00MHz to 200.00MHz) 5 ns max. (20%VDD to 80%VDD level) VOL : 10%VDD max. (1.00MHz to 130.00MHz) VOL : 20%VDD max. (130.00MHz to 200.00MHz) VOH : 90%VDD min. (1.00MHz to 130.00MHz) VOH : 80%VDD min. (130.00MHz to 200.00MHz) 15 pF max. (CMOS) 50 pF max. (CMOS) 100 ns max. 150 ns max.(OE models) 10 ms max.(Stand-by models) 10 ms max. 100, 200, 250 max. (depending on frequencies) ±5 ppm max. at +25˚C ±3˚C for first year +250˚C ±10˚C for 10 seconds +170˚C ±10˚C for 1 to 2 minutes (preheating) using PLL technology (※1) Final exact part number to be determined with frequency, frequency stability, operating temperature and input voltage. e.g. 91SMOP(3.3VA)SB 200.000 MHz. (※2) Internal crystal oscillation to continue(Pin #1=VIL). (※3) Internal crystal oscillation to be halted(Pin #1=VIL). Generic part number Frequency range Frequency stability (-20˚C to +75˚C) over all conditions Operating Conditions Operating temperature Input voltage (VDD) Tri-state control (Option1) OE control voltage (Pin#1)/(Pin#3) OPEN→Output VIH→Output VIL→High Impedance※2 Tri-state control (Option2) Stand-by (SB) control voltage (Pin#1)/(Pin#3) OPEN→Output VIH→Output VIL→High Impedance※3 Absolute Max. Ratings Supply voltage Storage temperature Input current +3.0V ±10% (Pin#1=Open or VIH) +3.0V ±10% +5V ±10% Stand-by current※3(option) Output (-20˚C to +75˚C) Symmetry Rise and fall times "0" level "1" level Load Disable delay time Enable delay time Startup time Jitter (pSp-p) Aging (non operating) Reflow condition (※2) Internal crystal oscillation to continue. (※3) Internal crystal oscillation to stop. A 7.4 5.4 16.0 7.5 8.0 1.5 0.3 1.9 180 1000pcs Qty/Reel B C D F J L M Reel Dia. 4.0 ±0.1 2.0 ±0.1 +0.1 -0 φ1.5 L B F J M TAPE SPECIFICATIONS Actual Size |
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