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OPA4650

FREQUENCY RESPONSE COMPENSATION

Each channel of the OPA4650 is internally compensated to

be stable at unity gain with a nominal 60

° phase margin.

This lends itself well to wideband integrator and buffer

applications. Phase margin and frequency response flatness

will improve at higher gains. Recall that an inverting gain of

–1 is equivalent to a gain of +2 for bandwidth purposes, i.e.,

noise gain = 2. The external compensation techniques devel-

oped for voltage feedback op amps can be applied to this

device. For example, in the non-inverting configuration,

placing a capacitor across the feedback resistor will reduce

the gain to +1 starting at f = (1/2

πR

inverting configuration, the bandwidth may be limited with-

out modifying the inverting gain by placing a series RC

network to ground on the inverting node. This has the effect

of increasing the noise gain at high frequencies, thereby

limiting the bandwidth for the inverting input signal through

the gain-bandwidth product.

At higher gains, the gain-bandwidth of this voltage feedback

topology will limit bandwidth according to the open-loop

frequency response curve. For applications requiring a wider

bandwidth at higher gains, consider the quad current feed-

back model, OPA4658. In applications where a large feed-

back resistor is required (such as photodiode transimpedance

circuits), precautions must be taken to avoid gain peaking

due to the pole formed by the feedback resistor and the

summing junction capacitance. This pole can be compen-

sated by connecting a small capacitor in parallel with the

feedback resistor, creating a cancelling zero term. In other

high-gain applications, use of a three-resistor “T” connec-

tion will reduce the feedback network impedance which

reacts with the parasitic capacitance at the summing node.

PULSE SETTLING TIME

High speed amplifiers like the OPA4650 are capable of

extremely fast settling time with a pulse input. Excellent

frequency response flatness and phase linearity are required

to get the best settling times. As shown in the specifications

table, settling time for a

±1V step at a gain of +1 for the

OPA4650 is extremely fast. The specification is defined as

the time required, after the input transition, for the output to

settle within a specified error band around its final value. For

a 2V step, 1% settling corresponds to an error band of

±20mV, 0.1% to an error band of ±2mV, and 0.01% to an

error band of

±0.2mV. For the best settling times, particu-

larly into an ADC capacitive load, little or no peaking in the

frequency response can be allowed. Using the recommended

the settling times. Fast, extremely fine scale settling (0.01%)

requires close attention to ground return currents in the

supply decoupling capacitors. For highest performance, con-

sider the OPA642 which isolates the output stage decoupling

from the rest of the amplifier.

THERMAL CONSIDERATIONS

The OPA4650 will not require heatsinking under most

operating conditions. Maximum desired junction tempera-

ture will limit the maximum allowed internal power dissipa-

tion as described below. In no case should the maximum

junction temperature be allowed to exceed +175

°C.

bination of the total quiescent power for all channels (P

and the sum of the powers dissipated in each of the output

stages (P

simply the specified no-load supply current times the total

supply voltage across the part. P

required output signal and load but would, for a grounded

resistive load, be at a maximum when the output is a fixed

dc voltage equal to 1/2 of either supply voltage (assuming

equal bipolar supplies). Under this condition, P

that it is the power dissipated in the output stage and not in

the load that determines internal power dissipation. As an

example, compute the maximum T

outputs at |V

Maximum T

DRIVING CAPACITIVE LOADS

The OPA4650’s output stage has been optimized to drive

low resistive loads. Capacitive loads will decrease phase

margin which may result in high frequency oscillations or

peaking. Capacitive loads greater than 10pF should be iso-

lated by connecting a small resistance (15

Ω to 30Ω) in series

with the output as shown in Figure 4. This is especially

important when driving the capacitive input of high-speed

A/D converters. Increasing the gain from +1 will improve

the capacitive load drive due to increased phase margin.

In general, capacitive loads should be minimized for opti-

mum high frequency performance. Coax lines can be driven

if the cable is properly terminated. The capacitance of coax

cable (29pF/ft for RG-58) will not load the amplifier when

the cable is source and load terminated in its characteristic

impedance.

FIGURE 4. Driving Capacitive Loads.

OPA4650

C

L

R

L

R

ISO

(R

25

Ω