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PGA206PA Datasheet(PDF) 7 Page - Burr-Brown (TI) |
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PGA206PA Datasheet(HTML) 7 Page - Burr-Brown (TI) |
7 / 10 page 7 ® PGA206/207 FIGURE 1. Basic Connections. APPLICATIONS INFORMATION Figure 1 shows the circuit diagram for basic operation of the PGA206 or PGA207. Applications with noisy or high im- pedance power supplies may require decoupling capacitors close to the device pins as shown. The output is referred to the output reference (Ref) terminal which is normally grounded. This must be a low-impedance connection to assure good common-mode rejection. A resis- tance of 2 Ω in series with the Ref pin will cause a typical device to degrade to approximately 80dB CMR (G = 1). The output sense connection (pin 12) must be connected to the output terminal (pin 11) for proper operation. This connection can be made at the load for best accuracy. DIGITAL INPUTS The digital inputs A0 and A1 select the gain according to the logic table in Figure 1. Logic “1” is defined as a voltage greater than 2V above digital ground potential (pin 14). Digital ground can be connected to any potential ranging from the V– power supply to 4V less than V+. Digital ground is usually equal to analog ground potential and the two grounds are connected at the power supply. The digital inputs interface directly to CMOS and TTL logic. A nearly constant current of approximately 1.2mA flows in the digital ground pin. It is good practice to return digital ground through a separate connection path so that analog ground is not affected by the digital ground current. A 1 A 2 A 3 12 11 10 10k Ω 10k Ω 10k Ω 10k Ω 7 5 14 16 4 V IN V IN PGA206 PGA207 V O = G (VIN – VIN) V O – + Over-Voltage Protection Over-Voltage Protection Sense Digitally Selected Feedback Network 113 V O1 15 6 9 8 V O2 V OS Adj +15V 1µF –15V 1µF +– PGA206 V IN V IN – + V O A 1 A0 Sometimes shown in simplified form: A 1 A0 PGA207 PGA206 GAIN 0 0 1 1 0 1 0 1 1 2 5 10 1 2 4 8 Ref Digital Ground The digital inputs, A 0 and A1, are not latched. A change in logic input immediately selects a new gain. Switching time of the logic is approximately 500ns. The time to respond to gain change is equal to switching time, plus the time it takes the amplifier to settle to a new output voltage in the newly selected gain (see settling time specifications). Many applications use an external logic latch to acquire gain control data from a high speed digital bus. Using an external latch isolates the high speed digital bus from sensitive analog circuitry. Locate the digital latch as far as practical from analog circuitry to avoid coupling digital noise into analog input circuitry. OFFSET VOLTAGE ADJUSTMENT The PGA206 and PGA207 are laser trimmed for very low offset voltage and drift. Many applications require no exter- nal offset adjustment. Multiplexed data acquisition systems generally correct offset by grounding the inputs of one channel to measure offset voltage. Stored offset values for each gain are then subtracted from subsequent readings of other channels. Figure 2 shows optional offset voltage trim circuits. Offset voltage changes with the selected gain. To adjust for low offset voltage in all gains, both input and output offsets must be trimmed. |
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