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EP1K100 Datasheet(PDF) 8 Page - Altera Corporation

Part # EP1K100
Description  Programmable Logic Device Family
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1K100 Datasheet(HTML) 8 Page - Altera Corporation

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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 1. ACEX 1K Device Block Diagram
ACEX 1K devices provide six dedicated inputs that drive the flipflops’
control inputs and ensure the efficient distribution of high-speed, low-
skew (less than 1.0 ns) control signals. These signals use dedicated routing
channels that provide shorter delays and lower skews than the FastTrack
Interconnect routing structure. Four of the dedicated inputs drive four
global signals. These four global signals can also be driven by internal
logic, providing an ideal solution for a clock divider or an internally
generated asynchronous clear signal that clears many registers in the
device.
I/O Element
(IOE)
Logic Array
Block (LAB)
Row
Interconnect
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Local Interconnect
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Logic Element (LE)
Column
Interconnect
IOE
EAB
EAB
Logic
Array
IOE
IOE
IOE
IOE
IOE
IOE
Embedded Array Block (EAB)
Embedded Array
IOE
IOE
Logic Array
IOE
IOE


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