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IDT821054PQFG Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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IDT821054PQFG Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
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7 / 45 page  7 IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE INDUSTRIAL TEMPERATURE RANGE 1 PIN DESCRIPTION Name Type Pin Number Description GNDA1 GNDA2 GNDA3 GNDA4 Ground 50 54 59 63 Analog Ground. All ground pins should be connected together. GNDD Ground 21 Digital Ground. All digital signals are referred to this pin. VDDA12 VDDA34 Power 52 61 +5 V Analog Power Supply. These pins should be connected to ground via a 0.1 µF capacitor. All power supply pins should be connected together. VDDD Power 24 +5 V Digital Power Supply. VDDB Power 57 +5 V Analog Power Supply. This pin should be connected to ground via a 0.1 µF capacitor. All power supply pins should be connected together. CNF − 56 Capacitor Noise Filter. This pin should be connected to ground via a 0.22 µF capacitor. VIN1-4 I 49, 55, 58, 64 Analog Voice Inputs of Channel 1-4. These pins should be connected to the corresponding SLIC via a 0.22 µF capacitor. VOUT1-4 O 51, 53, 60, 62 Voice Frequency Receiver Outputs of Channel 1-4. These pins can drive 300 Ω AC load. It can drive transformers directly. SI1_(1-4) SI2_(1-4) I 36, 47, 2, 13 35, 48, 1, 14 SLIC Signalling Inputs with debounce function for Channel 1-4. SB1_(1-4) SB2_(1-4) SB3_(1-4) I/O 39, 44, 5, 10 38, 45, 4, 11 37, 46, 3, 12 Bi-directional SLIC Signalling I/Os for Channel 1-4. These pins can be individually programmed as input or output. SO1_(1-4) SO2_(1-4) O 41, 42, 7, 8 40, 43, 6, 9 SLIC Signalling Outputs for Channel 1-4. DX1 O26 Transmit PCM Data Output, PCM Highway One. Transmit PCM Data to PCM highway one. This pin is a tri-state output pin. DX2 O29 Transmit PCM Data Output, PCM Highway Two. Transmit PCM Data to PCM highway two. This pin is a tri-state output pin. DR1 I27 Receive PCM Data Input, PCM Highway One. The PCM data is received from PCM highway one (DR1) or two (DR2). The receive PCM highway is selected by local register LREG6. DR2 I30 Receive PCM Data Input, PCM Highway Two. The PCM data is received from PCM highway one (DR1) or two (DR2). The receive PCM highway is selected by local register LREG6. FS I31 Frame Synchronization. FS is an 8 kHz synchronization clock that identifies the beginning of the PCM frame. BCLK I32 Bit Clock. This pin clocks out the PCM data to DX1 or DX2 pin and clocks in PCM data from DR1 or DR2 pin. It may vary from 512 kHz to 8.192 MHz and should be synchronous to FS. TSX1 TSX2 0 25 28 Transmit Output Indicator. The TSX1 pin becomes low when PCM data is transmitted via DX1. Open-drain. The TSX2 pin becomes low when PCM data is transmitted via DX2. Open-drain. |
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