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EPM7096 Datasheet(PDF) 10 Page - Altera Corporation |
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EPM7096 Datasheet(HTML) 10 Page - Altera Corporation |
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10 / 66 page  10 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 4 shows a MAX 7000E and MAX 7000S device macrocell. Figure 4. MAX 7000E & MAX 7000S Device Macrocell Combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. The product-term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocell’s register clear, preset, clock, and clock enable control functions. Two kinds of expander product terms (“expanders”) are available to supplement macrocell logic resources: ■ Shareable expanders, which are inverted product terms that are fed back into the logic array ■ Parallel expanders, which are product terms borrowed from adjacent macrocells The Altera development system automatically optimizes product-term allocation according to the logic requirements of the design. For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera development software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. Product- Term Select Matrix 36 Signals from PIA 16 Expander Product Terms Logic Array Parallel Logic Expanders (from other macrocells) Shared Logic Expanders Clear Select Global Clear Global Clocks Clock/ Enable Select 2 PRN CLRN D/T Q ENA Register Bypass to I/O Control Block to PIA Programmable Register from I/O pin Fast Input Select VCC |
Similar Part No. - EPM7096 |
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Similar Description - EPM7096 |
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