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74LS322 Datasheet(PDF) 2 Page - Motorola, Inc |
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74LS322 Datasheet(HTML) 2 Page - Motorola, Inc |
2 / 4 page 5-2 FAST AND LS TTL DATA SN54/74LS322A BLOCK DIAGRAM REGISTER ENABLE G S/P SIGN EXTEND SE D1 DATA SELECT DS D0 CLOCK CLEAR OUTPUT ENABLE OE (8) (9) (11) (3) (19) (18) (2) (1) (12) (13) (7) (16) (4) (17) CK D Q Q CLR CK D Q Q CLR CK D Q Q CLR CK D Q Q CLR A/QA B/QB G/QG H/QH FOUR IDENTICAL CHANNELS NOT SHOWN QH FUNCTION TABLE OPERATION INPUTS INPUTS/OUTPUTS OUTPUT QH′ OPERATION CLEAR REGISTER ENABLE S/P SIGN EXTEND DATA SELECT OUTPUT ENABLE CLOCK A/QA B/QB C/QC H/QH OUTPUT QH′ Clear L H X X X L X L L L L L L X H X X L X L L L L L Hold H H X X X L X QA0 QB0 QC0 QH0 QH0 Shift Right H L H H L L ↑ D0 QAn QBn QGn QGn Shift Right H L H H H L ↑ D1 QAn QBn QGn QGn Sign Extend H L H L X L ↑ QAn QAn QBn QGn QGn Load H L L X X X ↑ a b c h h When the output enable is high, the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected. If both the register enable input and the S/P input are low while the clear input is low, the register is cleared while the eight input/output terminals are disabled to the high-impedance state. H = HIGH Level (steady state) L = LOW Level (steady state) X = Irrelevant (any input, including transitions) ↑ = Transition from LOW to HIGH level QA0 …QH0 = the level of QA through QH, respectively, before the indicated steady-state conditions were established QAn …QHn = the level of QA through QH, respectively, before the most recent ↑ transition of the clock D0, D1 = the level of steady-state inputs at inputs D0 and D1 respectively a …h = the level of steady-state inputs at inputs A through H respectively … |
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