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OR2T40A-2S432 Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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OR2T40A-2S432 Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
7 / 192 page Lucent Technologies Inc. 7 Data Sheet June 1999 ORCA Series 2 FPGAs Programmable Logic Cells (continued) Table 3 lists the basic operating modes of the LUT. The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For example, in some operating modes, the WD[3:0] inputs are direct data inputs to the PFU latches/FFs. In the dual 16 x 2 memory mode, the same WD[3:0] inputs are used as a 4-bit data input bus into LUT memory. The PFU is used in a variety of modes, as illustrated in Figures 4 through 11, and it is these specific modes that are most relevant to PFU functionality. PFU Control Inputs The four control inputs to the PFU are clock (CK), local set/reset (LSR), clock enable (CE), and C0. The CK, CE, and LSR inputs control the operation of all four latches in the PFU. An active-low global set/reset (GSRN) signal is also available to the latches/FFs in every PFU. Their operation is discussed briefly here, and in more detail in the Latches/Flip-Flops section. The polarity of the control inputs can be inverted. The CK input is distributed to each PFU from a vertical or horizontal net. The CE input inhibits the latches/FFs from responding to data inputs. The CE input can be disabled, always enabling the clock. Each latch/FF can be independently programmed to be set or reset by the LSR and the global set/reset (GSRN) signals. Each PFU’s LSR input can be configured as synchronous or asynchronous. The GSRN signal is always asynchro- nous. The LSR signal applies to all four latches/FFs in a PFU. The LSR input can be disabled (the default). The asynchronous set/reset is dominant over clocked inputs. The C0 input is used as an input into the special PFU gates for wide functions in combinatorial logic mode. In the memory modes, this input is also used as the write-port enable input. The C0 input can be disabled (the default). Look-Up Table Operating Modes The look-up table (LUT) can be configured to operate in one of three general modes: s Combinatorial logic mode s Ripple mode s Memory mode The combinatorial logic mode uses a 64-bit look-up table to implement Boolean functions. The two 5-bit logic inputs, A[4:0] and B[4:0], and the C0 input are used as LUT inputs. The use of these ports changes based on the PFU operating mode. The functionality of the LUT is determined by its operat- ing mode. The entries in Table 3 show the basic modes of operation for combinatorial logic, ripple, and memory functions in the LUT. Depending on the operating mode, the LUT can be divided into sub-LUTs. The LUT is comprised of two 32-bit half look-up tables, HLUTA and HLUTB. Each half look-up table (HLUT) is com- prised of two quarter look-up tables (QLUTs). HLUTA consists of QLUT2 and QLUT3, while HLUTB consists of QLUT0 and QLUT1. The outputs of QLUT0, QLUT1, QLUT2, and QLUT3 are F0, F1, F2, and F3, respec- tively. Table 3. Look-Up Table Operating Modes For combinatorial logic, the LUT can be used to do any single function of six inputs, any two functions of five inputs, or four functions of four inputs (with some inputs shared), and three special functions based on the two five-input functions and C0. Mode Function F4A Two functions of four inputs, some inputs shared (QLUT2/QLUT3) F4B Two functions of four inputs, some inputs shared (QLUT0/QLUT1) F5A One function of five inputs (HLUTA) F5B One function of five inputs (HLUTB) R 4-bit ripple (LUT) MA 16 x 2 asynchronous memory (HLUTA) MB 16 x 2 asynchronous memory (HLUTB) SSPM 16 x 4 synchronous single-port memory SDPM 16 x 2 synchronous dual-port memory |
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