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5

AFL28XXD Series

Block Diagram

Figure II. Enable Input Equivalent Circuit

Circuit Operation and Application Information

The AFL series of converters employ a forward switched

mode converter topology. (refer to the block diagram in

Figure I.) Operation of the device is initiated when a DC

voltage whose magnitude is within the specified input voltage

limits is applied between pins 1 and 2. If pin 4 is enabled (at

a logical 1 or open) the primary bias supply will begin

generating a regulated housekeeping voltage bringing the

circuitry on the primary side of the converter to life. A power

MOSFET is used to chop the DC input voltage into a high

frequency square wave, applying this chopped voltage to

the power transformer at the nominal converter switching

frequency. By maintaining a DC voltage within specified

operating range at the input, continuous generation of the

bias voltage is assured.

The switched voltage impressed on the secondary output

transformer windings is rectified and filtered to provide the

positive and negative converter output voltages. An error

amplifier on the secondary side compares the positive output

voltage to a precision reference and generates an error

signal proportional to the difference. This error signal is

magnetically coupled through the feedback transformer into

the control section of the converter varying the pulse width

of the square wave signal driving the MOSFETs, narrowing

the pulse width if the output voltage is too high and widening

it if it is too low. These pulse width variations provide the

necessary corrections to regulate the magnitude of output

voltage within its’ specified limits.

Because the primary portion of the circuit is coupled to the

secondary side with magnetic elements, full isolation from

input to output is maintained.

Although incorporating several sophisticated and useful

ancilliary features, basic operation of the AFL28XXD series

series can be initiated by simply applying an input voltage to

pins 1 and 2 and connecting the appropriate loads between

pins 7, 8, and 9. As is the case with any high power density

converter, operation should not be initiated before secure

attachment to an appropriate heat dissipator. (See Thermal

Considerations, page 7) Additional application information

is provided in the paragraphs following.

Inhibiting Converter Output (Enable)

As an alternative to application and removal of the DC voltage

to the input, the user can control the converter output by

providing TTL compatible, positive logic signals to either of

two enable pins (pin 4 or 12). The distinction between these

two signal ports is that enable 1 (pin 4) is referenced to the

input return (pin 2) while enable 2 (pin 12) is referenced to

the output return (pin 8). Thus, the user has access to an

inhibit function on either side of the isolation barrier. Each

port is internally pulled “high” so that when not used, an

open connection on both enable pins permits normal

converter operation. When their use is desired, a logical

“low” on either port will shut the converter down.

Pin 4 or

Pin 12

1N4148

100K

200K

220K

2N3904

+5.6V

Disable

Pin 2 or

Pin 8

+ Input

Enable 1

Input

Filter

Sync Input

Primary

Bias Supply

Control

Sync Output

Input Return

Case

4

1

5

6

3

2

Error

Amp

& Ref

Output

Filter

Current

Sense

Output

Filter

Share

Amplifier

+ Output

Output Return

-Output

Share

Enable 2

Output Voltage

Trim

7

8

9

11

12

10

Figure I. Dual Output