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FDMF5820DCCT-ND Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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FDMF5820DCCT-ND Datasheet(HTML) 11 Page - Fairchild Semiconductor |
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11 / 25 page  © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF5820DC • Rev. 1.0.1 11 Functional Description The SPS FDMF5820DC is a driver-plus-MOSFET module optimized for the synchronous buck converter topology. A PWM input signal is required to properly drive the high-side and the low-side MOSFETs. The part is capable of driving speed up to 1.5 MHz. Power-On Reset (POR) The PWM input stage should incorporate a POR feature to ensure both LDRV and HDRV are forced inactive (LDRV = HDRV = 0) until UVLO > ~ 3.8 V (rising threshold). After all gate drive blocks are fully powered on and have finished the startup sequence, the internal driver IC EN_PWM signal is released HIGH, enabling the driver outputs. Once the driver POR has finished (<20 µs maximum), the driver follows the state of the PWM signal (it is assumed that at startup the controller is either in a high-impedance state or forcing the PWM signal to be within the driver 3-state window). Three conditions below must be supported for normal startup / power-up. VCC rises to 5 V, then EN goes HIGH; EN pin is tied to the VCC pin; EN is commanded HIGH prior to 5 V VCC reaching the UVLO rising threshold. The POR method is to increase the VCC over than UVLO > rising threshold and EN = HIGH. Under-Voltage Lockout (UVLO) UVLO is performed on VCC only, not on PVCC or VIN. When the EN is set HIGH and VCC is rising over the UVLO threshold level (3.8 V), the part starts switching operation after a maximum 20 µs POR delay. The delay is implemented to ensure the internal circuitry is biased, stable, and ready to operate. Two VCC pins are provided: PVCC and VCC. The gate driver circuitry is powered from the PVCC rail. The user connects PVCC to VCC through a low-pass R-C filter. This provides a filtered 5 V bias to the analog circuitry on the IC. Figure 26. UVLO on VCC EN / FAULT# (Enable / Fault Flag) The driver can be disabled by pulling the EN / FAULT# pin LOW (EN < VIL_EN), which holds both GL and GH LOW regardless of the PWM input state. The driver can be enabled by raising the EN / FAULT# pin voltage HIGH (EN > VIH_EN). The driver IC has less than 3 µA shutdown current when it is disabled. Once the driver is re-enabled, it takes a maximum of 20 µs startup time. EN / FAULT# pin is an open-drain output for fault flag with an internal 250 kΩ pull-down resistor. Logic HIGH signal from PWM controller or a ~ 10 kΩ external pull-up resistor from EN / FAULT# pin to VCC is required to start driver operation. Table 1. UVLO and Enable Logic UVLO EN Driver State 0 X Disabled (GH & GL = 0) 1 0 Disabled (GH & GL = 0) 1 1 Enabled (see Table 2) 1 Open Disabled (GH & GL = 0) The EN / FAULT# pin has two functions: enabling / disabling driver and fault flag. The fault flag signal is active LOW. When the driver detects a fault condition during operation, it turns on the open-drain on the EN / FAULT# pin and the pin voltage is pulled LOW. The fault conditions are: High-side MOSFET false turn-on or VIN ~ SW short during low-side MOSFET turn on; P-THDN by exceeding 1.5 V on TMON pin. When the driver detects a fault condition and disables itself, a POR event on VCC is required to restart the driver operation. 3-State PWM Input The FDMF5820DC incorporates a 3-state 3.3 V PWM input gate drive design. The 3-state gate drive has both logic HIGH and LOW levels, along with a 3-state shutdown window. When the PWM input signal enters and remains within the 3-state window for a defined hold-off time (tD_HOLD-OFF), both GL and GH are pulled LOW. This feature enables the gate drive to shut down both the high-side and the low-side MOSFETs to support features such as phase shedding, a common feature on multi-phase voltage regulators. Table 2. EN / PWM / 3-State / ZCD# Logic States EN PWM ZCD# GH GL 0 X X 0 0 1 3-State X 0 0 1 0 0 0 1 (IL > 0), 0 (IL < 0) 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 |
Similar Part No. - FDMF5820DCCT-ND |
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Similar Description - FDMF5820DCCT-ND |
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