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CAT28F002PI-90BT Datasheet(PDF) 9 Page - Catalyst Semiconductor |
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CAT28F002PI-90BT Datasheet(HTML) 9 Page - Catalyst Semiconductor |
9 / 16 page CAT28F002 9 Doc. No. 25072-00 2/98 F-1 WRITE OPERATIONS The following operations are initiated by observing the sequence specified in the Write Command Table. Read Array The device can be put into a Read Array Mode by initiating a write cycle with FFH on the data bus. The device is also in a standard Read Array Mode after the initial device power up and when comes out of the Deep Power-Down mode. Signature Mode An alternative method for reading device signature (see Read Operations Signature Mode), is initiated by writing the code 90H into the command register. A read cycle from address 0000H with CE and OE low (and WE high) will output the device signature. Catalyst Code = Catalyst Code = 0011 0001 (31H) A Read cycle from address 0001H retrieves the binary code for the device on outputs I/O7 to I/O0: CAT28F002T = 0111 1100 (7CH) CAT28F002B = 0111 1101 (7DH) To terminate the operations, it is necessary to write another valid command into the register. STATUS REGISTER The 28F002 contains an 8-bit Status Register. The Status Register is polled to check for write or erase completion or any related errors. The Status Register may be read at any time by issuing a Read Status Register (70H) command. All subsequent read opera- tions output data from the Status Register, until another valid command is issued. The contents of the Status Register are latched on the falling edge of OE or CE, whichever occurs last in the read cycle. OE or CE must be toggled to VIH before further reads to update the status register latch. The Erase Status (SR.5) and Program Status (SR.4) are set to 1 by the WSM and can only be reset issuing Clear Status Register (50H) These two bits can be polled for failures, thus allowing more flexibility to the designer when using the CAT28F002. Also, VPP Status (SR.3) when set to 1 must be reset by system software before any further byte programs or block erases are attempted. ERASE SETUP/ERASE CONFIRM Erase is executed one block at a time, initiated by a two cycle command sequence. The two cycle command sequence provides added security against accidental block erasure. During the first write cycle, a Command 20H (Erase Setup) is first written to the Command Register, followed by the Command D0H (Erase Con- firm). These commands require both appropriate com- mand data and an address within Block to be erased. Also, Block erasure can only occur when VPP= VPPH. Block preconditioning, erase and verify are all handled internally by the Write State Machine, invisible to the system. After receiving the two command erase se- quence the CAT28F002 automatically outputs Status Register data when read (Fig.5). The CPU can detect the completion of the erase event by checking if the SR.7 of the Status Register is set. SR.5 will indicate whether the erase was successful. If an erase error is detected, the Status Register should be cleared. The device will be in the Status Register Read Mode until another command is issued. ERASE SUSPEND/ERASE RESUME The Erase Suspend Command allows erase sequence interruption in order to read data from another block of memory. Once the erase sequence is started, writing the Erase Suspend command (B0H) to the Command Register requests that the WSM suspend the erase sequence at a predetermined point in the erase algo- rithm. The CAT28F002 continues to output Status Reg- ister data when read, after the Erase Suspend command is written to it. Polling the WSM Status and Erase Suspend Status bits will determine when the erase operation has been suspended (both will be set to “1s”). The device may now be given a Read ARRAY Com- mand, which allows any locations 'not within the block being erased' to be read. Also, you can either perform a Read Status Register or resume the Erase Operation by sending Erase Resume (D0H), at which time the WSM will continue with the erase sequence. The Erase Suspend Status and WSM Status bits of the Status Register will be cleared. PROGRAM SETUP/PROGRAM COMMANDS Programming is executed by a two-write sequence. The program Setup command (40H) is written to the Com- mand Register, followed by a second write specifying the address and data (latched on the rising edge of WE) to be programmed. The WSM then takes over, control- ling the program and verify algorithms internally. After the two-command program sequence is written to it, the CAT28F002 automatically outputs Status Register data when read (see figure 4; Byte Program Flowchart). The CPU can detect the completion of the program event by analyzing the WSM Status bit of the Status Register. Only the Read Status Register Command is valid while programming is active. |
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