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CAT35C704JITE13 Datasheet(PDF) 7 Page - Catalyst Semiconductor |
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CAT35C704JITE13 Datasheet(HTML) 7 Page - Catalyst Semiconductor |
7 / 14 page Preliminary CAT35C704 7 Doc. No. 25045-00 2/98 also go to the high impedance state if an error condition is detected. If the ENABLE BUSY instruction has not been executed, to determine whether the device is in a program/erase cycle or in an error condition, a READ STATUS instruction may be entered. When the device is in a program/erase cycle it will output an 8-bit status word. If it does not, it is in an error condition. PE The Parity Enable pin is a TTL compatible input. If the PE pin is set HIGH, the device will be configured to commu- nicate using even parity, and if the pin is set LOW, it will use no parity. In this case, instructions or data that include parity bits will not be interpreted correctly. Note: The PE input is internally pulled down to GND (i.e. default = no parity). As with all CMOS devices, CS, CLK and DI inputs must be connected to either HIGH or LOW, and not left floating. ERR The Error indication pin is an open drain output. If either an instruction or parity error exists, the ERR pin will output a “0” until the device is reset. This can be done by pulsing CS LOW. 5074 FHD F10 Figure 8. Write Timing 5074 FHD F11 Figure 7. Read Timing CS CLK DI HIGH-Z DO OP7 AN OP0 A0 DN D0 tPD tHZ OP CODE ADDRESS VCC DATA CS CLK DI DO OP7 AN OP0 A0 tSV OP CODE ADDRESS DN D0 DON’T CARE DATA tEW BUSY READY |
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