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SN74LS85N Datasheet(PDF) 3 Page - Motorola, Inc |
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SN74LS85N Datasheet(HTML) 3 Page - Motorola, Inc |
3 / 4 page NOTE: The SN54/74LS85 can be used as a 5-bit comparator only when the outputs are used to drive the A0–A3 and B0–B3 inputs of another SN54/74LS85 as shown in Figure 2 in positions #1, 2, 3, and 4. 5-86 FAST AND LS TTL DATA SN54/74LS85 Figure 1. Comparing Two n-Bit Words L = LOW LEVEL H = HIGH LEVEL A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 L L H IA > B IA < B IA = B OA > B OA < B OA = B IA > B IA < B IA = B OA > B OA < B OA = B A > B A < B A = B SN54/74LS85 SN54/74LS85 APPLICATIONS Figure 2 shows a high speed method of comparing two 24-bit words with only two levels of device delay. With the technique shown in Figure 1, six levels of device delay result when comparing two 24-bit words. The parallel technique can be expanded to any number of bits, see Table 1. Table 1 WORD LENGTH NUMBER OF PKGS. 1 – 4 Bits 1 5 – 24 Bits 2 – 6 25 – 120 Bits 8 – 31 MSB = MOST SIGNIFICANT BIT LSB = LEAST SIGNIFICANT BIT L = LOW LEVEL H = HIGH LEVEL NC = NO CONNECTION A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 L L H IA > B IA < B IA = B OA > B OA < B OA = B #5 (LSB) INPUTS A0 A1 A2 A3 B0 B1 B2 B3 IA > B IA < B IA = B OA > B OA < B OA = B #1 L NC A20 A21 B23 B22 B21 B20 A23 A22 A19 B19 (MSB) A5 A6 A7 A8 B5 B6 B7 B8 A0 A1 A2 A3 B0 B1 B2 B3 IA > B IA < B IA = B OA > B OA < B OA = B #4 NC L A4 B4 A0 A1 A2 A3 B0 B1 B2 B3 IA > B IA < B IA = B OA > B OA < B OA = B #3 NC L A9 B9 A10 A11 B13 B12 B11 B10 A13 A12 A0 A1 A2 A3 B0 B1 B2 B3 IA > B IA < B IA = B OA > B OA < B OA = B #2 NC L A14 B14 A15 A16 B18 B17 B16 B15 A18 A17 OUTPUTS A0 A1 A2 A3 B0 B1 B2 B3 IA > B IA < B IA = B OA > B OA < B OA = B #6 INPUTS Figure 2. Comparison of Two 24-Bit Words |
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