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AT24C256-10PU-1.8 Datasheet(PDF) 1 Page - ATMEL Corporation |
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AT24C256-10PU-1.8 Datasheet(HTML) 1 Page - ATMEL Corporation |
1 / 23 page 1 Features • Low-voltage and Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 3.6V) • Internally Organized 16,384 x 8 and 32,768 x 8 • Two-wire Serial Interface • Schmitt Trigger, Filtered Inputs for Noise Suppression • Bidirectional Data Transfer Protocol • 1 MHz (5V), 400 kHz (2.7V, 2.5V) and 100 kHz (1.8V) Compatibility • Write Protect Pin for Hardware and Software Data Protection • 64-byte Page Write Mode (Partial Page Writes Allowed) • Self-timed Write Cycle (5 ms Max) • High Reliability – Endurance: One Million Write Cycles – Data Retention: 40 Years • Extended Temperature and Lead-free/Halogen-free Devices Available • 8-lead JEDEC PDIP, 8-lead JEDEC and EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, 8-lead SAP and 8-ball dBGA2 Packages • Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers Description The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device’s cascadable feature allows up to 4 devices to share a common Two-wire bus. The device is optimized for use in many industrial and commercial appli- cations where low power and low voltage operation are essential. The devices are available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP (24C128), 8-lead TSSOP, 8-lead SOIC Array Package and 8-ball dBGA2 packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions. Table 1. Pin Configuration Pin Name Function A0 - A1 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NC No Connect GND Ground 8-lead SAP Bottom View 1 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 NC GND Two-wire Serial EEPROMs 128K (16,384 x 8) 256K (32,768 x 8) AT24C128(1) AT24C256(2) Notes: 1. Not recommended for new design; please refer to AT24C128B datasheet. 2. Not recommended for new design; please refer to AT24C256B datasheet. 0670T–SEEPR–3/07 8-lead PDIP 1 2 3 4 8 7 6 5 A0 A1 NC GND VCC WP SCL SDA 8-lead SOIC 1 2 3 4 8 7 6 5 A0 A1 NC GND VCC WP SCL SDA 8-ball dBGA2 Bottom View VCC WP SCL SDA A0 A1 NC GND 1 2 3 4 8 7 6 5 8-lead TSSOP 1 2 3 4 8 7 6 5 A0 A1 NC GND VCC WP SCL SDA 8-lead MAP Bottom View 1 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 NC GND |
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