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AT49F8192AT-12CC Datasheet(PDF) 5 Page - ATMEL Corporation

Part # AT49F8192AT-12CC
Description  8-megabit (1M x 8/512K x 16) Flash Memory
Download  17 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT49F8192AT-12CC Datasheet(HTML) 5 Page - ATMEL Corporation

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AT49F008A(T)/8192A(T)
5
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F008A(T)/8192A(T) features
DATA polling to indicate the end of a program cycle. During
a program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.
DATA polling may begin at any time during the program
cycle.
TOG G LE BI T: In addit i on to D ATA po lling the
AT49F008A(T)/8192A(T) provides another method for
determining the end of a program or erase cycle. During a
program or erase operation, successive attempts to read
data from the device will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
READY/BUSY: For the AT49F008A(T), pin 12 is an open
drain READY/BUSY output pin which provides another
method of detecting the end of a program or erase opera-
tion. RDY/BUSY is actively pulled low during the internal
program and erase cycles and it is released at the comple-
tion of the cycle. The open drain connection allows for OR-
tying of several devices to the same RDY/BUSY line.
HARDWARE DATA PROTECTION: Hardware features
pr ot ect ag ainst ina d ver t e n t pr og r a ms t o the
AT49F008A(T)/8192A(T) in the following ways: (a) VCC
sense: if V
CC is below 3.8V (typical), the program function
is inhibited. (b) V
CC power on delay: once VCC has reached
the V
CC sense level, the device will automatically time out
10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
AT49F008A(T) ALTERNATE PIN DEFINITION: Two
AT49F008A(T) BGA pin definitions are shown. The stan-
dard pin definition allows use of the JEDEC standard pro-
gramming algorithm. If the alternate pin definition is used,
the programming algorithm must be modified as shown in
the Command Definition for Alternate Pin Definition Table
on page 7.


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