CY7C1041DV33

Document Number: 38-05473 Rev. *K

Page 8 of 18

Figure 5. Read Cycle No. 2 (OE Controlled)[17, 18]

Figure 6. Write Cycle No. 1 (CE Controlled)[19, 20]

50%

50%

DATA VALID

HIGH IMPEDANCE

HIGH

OE

CE

ICC

ISB

IMPEDANCE

ADDRESS

DATA OUT

SUPPLY

BHE, BLE

CURRENT

BW

DATAI/O

ADDRESS

CE

WE

BHE, BLE

t

Notes

17. WE is HIGH for read cycle.

18. Address valid prior to or coincident with CE transition LOW.

20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

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