CY7C1041DV33

Document Number: 38-05473 Rev. *K

Page 6 of 18

AC Switching Characteristics

Over the Operating Range[6]

Parameter

Description

–10

(Industrial)

Unit

Min

Max

Read Cycle

100

–

s

Read cycle time

10

–

ns

Address to data valid

–

10

ns

Data hold from address change

3

–

ns

CE LOW to data valid

–

10

ns

OE LOW to data valid

–

5

ns

OE LOW to low Z[8]

0–

ns

OE HIGH to high Z[8, 9]

–5

ns

CE LOW to low Z[8]

3–

ns

CE HIGH to high Z[8, 9]

–5

ns

CE LOW to power-up

0

–

ns

CE HIGH to power-down

–

10

ns

Byte enable to data valid

–

5

ns

Byte enable to low Z

0

–

ns

Byte disable to high Z

–

6

ns

Write Cycle[10, 11]

Write cycle time

10

–

ns

CE LOW to write end

7

–

ns

Address setup to write end

7

–

ns

Address hold from write end

0

–

ns

Address setup to write start

0

–

ns

WE pulse width

7–

ns

Data setup to write end

5

–

ns

Data hold from write end

0

–

ns

WE HIGH to low Z[8]

3–

ns

WE LOW to high Z[8, 9]

–5

ns

Byte enable to end of write

7

–

ns

Notes

and 30-pF load capacitance.

device.

enter a high impedance state.

10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write and the transition of either of

these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.

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