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CY7C1041DV33-10BVJXI Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY7C1041DV33-10BVJXI Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 19 page  CY7C1041DV33 4-Mbit (256 K × 16) Static RAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-05473 Rev. *K Revised June 1, 2011 4-Mbit (256 K × 16) Static RAM Features ■ Temperature ranges ❐ Industrial: –40 °C to 85 °C ■ Pin and function compatible with CY7C1041CV33 ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 90 mA ■ Low CMOS standby power ❐ ISB2 = 10 mA ■ 2.0 V data retention ■ Automatic power-down when deselected ■ TTL compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded SOJ, and 44-pin TSOP II Packages Functional Description The CY7C1041DV33 is a high performance CMOS Static RAM organized as 256 K words by 16-bits. To write to the device, take chip enable (CE) and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O0 to I/O7) is written into the location specified on the address pins (A0 to A17). If byte high enable (BHE) is LOW, then data from I/O pins (I/O8 to I/O15) is written into the location specified on the address pins (A0 to A17). To read from the device, take chip enable (CE) and output enable (OE) LOW while forcing the write enable (WE) HIGH. If BLE is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If BHE is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 10 for a complete description of read and write modes. The input and output pins (I/O0 to I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). The CY7C1041DV33 is available in a standard 44-pin 400-mil wide SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout and a 48-ball FBGA package. A1 A2 A3 A4 A5 A6 A7 A8 COLUMN DECODER INPUT BUFFER 256K × 16 A0 IO0–IO7 OE IO8–IO15 CE WE BLE BHE Logic Block Diagram [+] Feedback |
Similar Part No. - CY7C1041DV33-10BVJXI |
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