__________ Applications Information

In addition to issuing a reset to the µP during power-up,

power-down, and brownout conditions, the MAX811/

MAX812 are relatively immune to short duration nega-

Figure 1 shows typical transient durations vs. reset

comparator overdrive, for which the MAX811/MAX812

do not generate a reset pulse. This graph was generat-

ing above the actual reset threshold and ending below

it by the magnitude indicated (reset comparator over-

drive). The graph indicates the typical maximum pulse

causing a reset pulse to be issued. As the magnitude

of the transient increases (goes farther below the reset

threshold), the maximum allowable pulse width

below the reset threshold and lasts 40µs or less

(MAX81_L/M) or 20µs or less (MAX81_T/S/R) will not

cause a reset pulse to be issued. A 0.1µF capacitor

tional transient immunity.

Ensuring a Valid RESET Output

no longer sinks current—it becomes an open circuit.

Therefore, high-impedance CMOS-logic inputs con-

nected to the RESET output can drift to undetermined

voltages. This presents no problem in most applica-

tions, since most µP and other circuitry is inoperative

RESET output must be valid down to 0V, adding a pull-

down resistor to the RESET pin will cause any stray

leakage currents to flow to ground, holding RESET low

(Figure 2). R1’s value is not critical; 100k

Ω is large

enough not to load RESET and small enough to pull

RESET to ground.

A 100k

for the MAX812 if RESET is required to remain valid for

4-Pin µP Voltage Monitors

with Manual Reset Input

6

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5

6

7

8

4

0

1

100

1000

2

1

3

10

°C

MAX81 _L/M

MAX81 _R/S/T

R1

GND

MAX811

RESET

Figure 1. Maximum Transient Duration without Causing a

Reset Pulse vs. Comparator Overdrive