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MX25L6408EZNI12G Datasheet(PDF) 10 Page - Macronix International

Part # MX25L6408EZNI12G
Description  64M-BIT [x 1 / x 2] CMOS SERIAL FLASH
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Manufacturer  MCNIX [Macronix International]
Direct Link  http://www.macronix.com
Logo MCNIX - Macronix International

MX25L6408EZNI12G Datasheet(HTML) 10 Page - Macronix International

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P/N: PM1643
REV. 1.4, DEC. 09, 2013
MX25L6408E
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended opera-
tion.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. The CS# falling time needs to
follow tCHCL spec.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge. The CS# rising time needs to follow tCLCH spec.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown in Figure 1.
5. For the following instructions:RDID, RDSR, RDSCUR, READ, FAST_READ, DREAD, RES, and REMS the shift-
ed-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS#
can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP, DP, ENSA, EXSA,and
WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not
executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
ed and not affect the current operation of Write Status Register, Program, Erase.
Figure 1.
Serial Modes Supported
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
SCLK
MSB
CPHA
shift in
shift out
SI
0
1
CPOL
0
(Serial mode 0)
(Serial mode 3) 1
SO
SCLK
MSB


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