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Datasheet

Datasheet

BU16501KS2

© 2013 ROHM Co., Ltd. All rights reserved.

www.rohm.com

TSZ22111・15・001

TSZ02201-0G3G0CZ00250-1-2

01.Oct.2013 Rev.001

Serial Interface - continued

(3) START and STOP condition

When SDA and SCL are H, data is not transferred on the I

while SCL has been H, it will become START (S) conditions, and an access start, if SDA changes from L to H while SCL

has been H, it will become STOP (P) conditions and an access end.

SDA

SCL

S

P

START condition

STOP condition

Figure 5. START/STOP condition (I

(4) Acknowledge

It transfers data 8 bits each after the occurrence of START condition. A transmitter opens SDA after transfer 8bits data,

and a receiver returns the acknowledge signal by setting SDA to L.

12

8

9

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

acknowledge

not acknowledge

S

START condition

clock pulse for

acknowledgement

SCL

Figure 6.

Acknowledge (I

(5) Writing protocol

A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The

3rd byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register

address is carried out automatically. However, when a register address turns into the last address (40h), it is set to 00h

by the next transmission. After the transmission end, the increment of the address is carried out.

S

A

A

A P

register address

slave address

from master to slave

from slave to master

R/W=0(write)

DATA

A

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

A7 A6 A5 A4 A3 A2 A1 A0

0

X X X X X X X

*1

*1

DATA

A=acknowledge(SDA LOW)

A=not acknowledge(SDA HIGH)

S=START condition

P=STOP condition

*1: Write Timing

register address

increment

register address

increment

(6) Timing diagram

SDA

SCL

S

Sr

P

S

Figure 7.

Timing diagram ( I