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MX25L6465EM2I10G Datasheet(PDF) 10 Page - Macronix International |
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MX25L6465EM2I10G Datasheet(HTML) 10 Page - Macronix International |
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10 / 85 page  10 MX25L6465E MX25L12865E P/N: PM1557 REV. 1.4, FEB. 10, 2012 DATA PROTECTION MX25L6465E/12865E is designed to offer protection against accidental erasure or programming caused by spuri- ous system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or sys- tem noise. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP, 4PP) command completion - Continuously Program mode (CP) instruction completion - Sector Erase (SE) command completion - Block Erase (BE, BE32K) command completion - Chip Erase (CE) command completion - Single Block Lock/Unlock (SBLK/SBULK) instruction completion - Gang Block Lock/Unlock (GBLK/GBULK) instruction completion • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Sig- nature command (RES). I. Block lock protection - The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "Protect- ed Area Sizes". - The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit. If the system goes into four I/O mode, the feature of HPM will be disabled. - MX25L6465E/12865E provide individual block (or sector) write protect & unprotect. User may enter the mode with WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with GBLK instruction and unlock the whole chip with GBULK instruction. |
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