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MX25L6465EZNI10G Datasheet(PDF) 7 Page - Macronix International |
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MX25L6465EZNI10G Datasheet(HTML) 7 Page - Macronix International |
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7 / 85 page  7 MX25L6465E MX25L12865E P/N: PM1557 REV. 1.4, FEB. 10, 2012 Table 1. Additional Features GENERAL DESCRIPTION MX25L6465E is 67,108,864 bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in two or four I/O mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. MX25L12865E is 134,217,728 bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When it is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. The MX25L6465E/12865E features a se- rial peripheral interface and software protocol allowing operation on a simple 4-wire bus. The four bus signals are a clock input (SCLK), a serial data input (SI), a serial data output (SO), and a chip select (CS#). Serial access to the device is enabled by CS# input. MX25L6465E/12865E provides high performance read mode, which may latch address and data on both rising and falling edge of clock. By using this high performance read mode, the data throughput may be doubling. Moreover, the performance may reach direct code execution, the RAM size of the system may be reduced and further saving system cost. MX25L6465E/12865E, MXSMIOTM (Serial Multi I/O) flash memory, provides sequential read operation on whole chip and multi-I/O features. When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data Input/Output. Parallel mode is also provided in this device. It features 8 bit input/output for increasing throughputs. This feature is recommeded to be used for factory production purpose. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte), block (32K-byte/64K-byte), or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 100uA DC cur- rent. The MX25L6465E/12865E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. Additional Features Part Name Protection and Security Read Performance Flexible or Individual block (or sector) protection 4K-bit secured OTP 1 I/O Read (104 MHz) 2 I/O Read (70 MHz) 4 I/O Read (70 MHz) 1 I/O DT Read (50 MHz) 2 I/O DT Read (50 MHz) 4 I/O DT Read (50 MHz) 8 I/O Parallel Mode (6 MHz) MX25L6465E MX25L12865E V V V V V V V V V (Note 1) Additional Features Part Name Identifier RES (command: AB hex) REMS (command: 90 hex) REMS2 (command: EF hex) REMS4 (command: DF hex) REMS4D (command: CF hex) RDID (command: 9F hex) MX25L6465E 16 (hex) C2 16 (hex) C2 16 (hex) C2 16 (hex) C2 16 (hex) C2 20 17 (hex) MX25L12865E 17 (hex) C2 17 (hex) C2 17 (hex) C2 17 (hex) C2 17 (hex) C2 20 18 (hex) Note 1: Only MX25L12865E provide parallel mode. |
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