TCA5600 TCF5600

10

MOTOROLA ANALOG IC DEVICE DATA

Programmable Voltage Regulator

This series voltage regulator is programmable by the

voltage divider R4, R5 for a nominal output voltage of 6.0 V

≤

Vout2 ≤ 30 V.

(7)

R4 =

[R5 = 10 k, Vref nom = 2.5 V]

Vref nom

Current limitation and thermal shutdown capability are

standard features of this regulator. The voltage drop

∆V(Pin 9 – Pin 8) across the series pass transistor generates

the feedback signal to control the dc/dc converter

(see Figure 13).

Control Inputs INH1, INH2

The dc/dc converter and/or the regulator Vout2 are remote

controllable through the TTL, MOS compatible inhibit inputs

INH1 and INH2 where the latter is a three–level detector

(Logic “0”, High Impedance “Z”, Logic “1”). Both inputs are

set–up to provide the following truth table:

Figure 15. INH1, INH2 TruthTable

Mode

INH1

INH2

Vout2

DC/DC

1

0

0

OFF

INT

2

0

High “Z”

Vout2

ON

3

0

1

Vout2

INT

4

1

0

OFF

INT

5

1

High “Z”

5.0 V

ON

6

1

1

5.0 V

INT

INT:

Intermittent operation of the converter means that the

converter operates only if VCC2<Vout2.

ON:

The converter loads the storage capacitor C2 to its full

charge (V9 = 33 V), allowing fast response time of the

regulator Vout2 when addressed by the control software.

OFF:

High impedance (internal resistor 10 k to ground)

Figure 16 represents a typical timing diagram for an E2PROM

programming sequence in a microprocessor based system.

The High “Z” state enables the dc/dc converter to ramp during

t3 to the voltage V9 at Pin 9 to a high level before the write

cycle takes place in the memory.

V9

VCC2

V9 max

– VF

Vout2

5.0V

INH1

“1”

”0”

INH2

“1”

“0”

High “Z”

t3

t4

V9 int

t

Programming

Voltage VPP

Figure 16. Typical E2PROM Programming Sequence

(not to scale)

Microprocessor Supply Regulator

Together with an external PNP power transistor (Q1), a

5.0 V supply exhibiting low voltage drop is obtained to power

microprocessor systems and auxiliary circuits. Using a power

Darlington with adequate heat sink in the output stage boosts

the output current Iout1 above 1.0 A.

The current limitation circuit measures the emitter current

of Q1 by means of the sensing resistor, RSC:

(8)

RSC =

VRSC

IE

[IE: emitter current of Q1]

[VRSC: threshold voltage

The voltage protection circuit performs a foldback

characteristic above a nominal operating voltage, VCC2 ≥

18 V.

Delay and Watchdog Circuit

The undervoltage monitor supervises the power supply

Vout1 and releases the delay circuit RESET as soon as the

regulator output reaches the microprocessor operating a

an open–collector and may be connected in a “wired–OR”

configuration.

The watchdog circuit consists of a retriggerable

monostable with a negative edge sensitive control input WDI.

The watchdog feature may be disabled by means of the

watchdog select input WDS driven to a “1”. Figure 17 displays

the Typical RESET Timing Diagram.

The commuted current source IC5 on Pin 17, threshold

voltage VC5(L), VC5(H) and an external capacitor C5 define

the RESET delay and the watchdog timing. The relationship

of the timing signals are indicated by the Equations (9) to (11).

(9)

RESET delay:

td =

C5

|IC5|

Watchdog timeout:

Watchdog RESET:

twd =

tr =

C5

5

C5

50

(10)

(11)

[IC5, VC5(H), VC5(L): see Electrical Characteristics Table]