MX25U8033EZNI12G datasheet(6/70 Pages) MCNIX

Part #	MX25U8033EZNI12G

Description	8M-BIT [x 1/x 2/x 4] 1.8V CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY

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Manufacturer	MCNIX [Macronix International]

Direct Link	http://www.macronix.com

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6

MX25U8033E

6

P/N: PM1718

REV. 1.4, NOV. 06, 2013

• Status Register Feature

• Electronic Identification

- JEDEC 1-byte manufacturer ID and 2-byte device ID

- RES command for 1-byte Device ID

- REMS, REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID

• Support Serial Flash Discoverable Parameter (SFDP) mode

HARDWARE FEATURES

• SCLK Input

- Serial clock input

• SI/SIO0

- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

• SO/SIO1

- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

• WP#/SIO2

- Hardware write protection or serial data Input/Output for 4 x I/O read mode

• HOLD#/SIO3

- HOLD feature, to pause the device without deselecting the device or serial data Input/Output for 4 x I/O read

mode

• PACKAGE

- 8-land USON (4x4mm)

- 8-pin SOP (150mil)

- 8-pin SOP (200mil)

- 8-land WSON (6x5mm)

-

All devices are RoHS Compliant and Halogen-free

GENERAL DESCRIPTION

The MX25U8033E is 8,388,608 bit serial Flash memory, which is configured as 1,048,576 x 8 internally. The

MX25U8033E features a serial peripheral interface and software protocol allowing operation on a simple 4-wire bus

while it is in single I/O mode. The four bus signals are a clock input (SCLK), a serial data input (SI), a serial data

output (SO) and a chip select (CS#). Serial access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits

input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0

pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX25U8033E MXSMIO (Serial Multi I/O) provides sequential read operation on the whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the

specified page or sector/block locations will be executed. Program command is executed on byte basis, or page

(256 bytes) basis. Erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or whole chip

basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via the WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for

more details.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX25U8033E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after

100,000 program and erase cycles.

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MX25U8033EZNI12G Datasheet(PDF) 6 Page - Macronix International

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