MX25U12835FZ2I10G datasheet(6/96 Pages) MCNIX

Part #	MX25U12835FZ2I10G

Description	1.8V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO짰 (SERIAL MULTI I/O) FLASH MEMORY

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Manufacturer	MCNIX [Macronix International]

Direct Link	http://www.macronix.com

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MX25U12835F

REV. 1.4, FEB. 12, 2014

P/N: PM1728

2. GENERAL DESCRIPTION

MX25U12835F is 128Mb bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When it is in

two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. MX25U12835F features a

serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O

mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial

access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits in-

put and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and Reset# pin become SIO0

pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX25U12835F MXSMIO® (Serial Multi I/O) provides sequential read operation on whole chip.

After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the

specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256

bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),

or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for

more details.

The MX25U12835F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after

100,000 program and erase cycles.

Table 1. Read Performance

MX25U12835F

Read Performance

SPI

QPI

I/O

1 I/O

1I /2O

2 I/O

1I/4O

4 I/O

Dummy Cycle

8

4

8

6

8

4

6

8

MHz

104 MHz 104MHz 84 MHz 104MHz 104 MHz 133 MHz* 84 MHz 104 MHz 133 MHz*

* For MX25U12835FZNI-08G only

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