MX25U25635FZ4I10G datasheet(10/96 Pages) MCNIX

Part #	MX25U25635FZ4I10G

Description	1.8V 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY

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Manufacturer	MCNIX [Macronix International]

Direct Link	http://www.macronix.com

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MX25U25635F

REV. 1.2, NOV. 28, 2013

P/N: PM1712

Table 2. Protected Area Sizes

Status bit

Protect Level

BP3

BP2

BP1

BP0

256Mb

0

0 (none)

0

1

1 (1 block, protected block 511st)

0

1

0

2 (2 blocks, protected block 510th~511st)

0

1

3 (4 blocks, protected block 508th~511st)

0

1

0

4 (8 blocks, protected block 504th~511st)

0

1

0

1

5 (16 blocks, protected block 496th~511st)

0

1

0

6 (32 blocks, protected block 480th~511st)

0

1

7 (64 blocks, protected block 448th~511st)

1

0

8 (128 blocks, protected block 384th~511st)

1

0

1

9 (256 blocks, protected block 256th~511st)

1

0

1

0

10 (512 blocks, protected all)

1

0

1

11 (512 blocks, protected all)

1

0

12 (512 blocks, protected all)

1

0

1

13 (512 blocks, protected all)

1

0

14 (512 blocks, protected all)

1

15 (512 blocks, protected all)

Status bit

Protect Level

BP3

BP2

BP1

BP0

256Mb

0

0 (none)

0

1

1 (1 block, protected block 0th)

0

1

0

2 (2 blocks, protected block 0th~1th)

0

1

3 (4 blocks, protected block 0th~3rd)

0

1

0

4 (8 blocks, protected block 0th~7th)

0

1

0

1

5 (16 blocks, protected block 0th~15th)

0

1

0

6 (32 blocks, protected block 0th~31st)

0

1

7 (64 blocks, protected block 0th~63rd)

1

0

8 (128 blocks, protected block 0th~127th)

1

0

1

9 (256 blocks, protected block 0th~255th)

1

0

1

0

10 (512 blocks, protected all)

1

0

1

11 (512 blocks, protected all)

1

0

12 (512 blocks, protected all)

1

0

1

13 (512 blocks, protected all)

1

0

14 (512 blocks, protected all)

1

15 (512 blocks, protected all)

Protected Area Sizes (T/B bit = 1)

Protected Area Sizes (T/B bit = 0)

I. Block lock protection

- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be

protected as read only. The protected area definition is shown as Table 2 Protected Area Sizes, the protected ar-

eas are more flexible which may protect various area by setting value of BP0-BP3 bits.

- The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status Reg-

ister Write Protect bit.

- In four I/O and QPI mode, the feature of HPM will be disabled.

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MX25U25635FZ4I10G Datasheet(PDF) 10 Page - Macronix International

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