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MX68GL1G0FUXFI12G Datasheet(PDF) 7 Page - Macronix International |
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MX68GL1G0FUXFI12G Datasheet(HTML) 7 Page - Macronix International |
7 / 71 page 7 P/N:PM1727 REV. 1.3, OCT. 30, 2013 MX68GL1G0F 3. PIN DESCRIPTION SYMBOL PIN NAME A0~A25 Address Input Q0~Q14 Data Inputs/Outputs Q15/A-1 Q15(Word Mode)/LSB addr(Byte Mode) CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input RESET# Hardware Reset Pin, Active Low WP#/ACC* Hardware Write Protect/Programming Acceleration input RY/BY# Ready/Busy Output BYTE# Selects 8 bits or 16 bits mode VCC +3.0V single power supply GND Device Ground NC Not Connected VI/O Power Supply for Input/Output LOGIC SYMBOL 16 or 8 Q0-Q15 (A-1) RY/BY# A0-A25 CE# OE# WE# RESET# WP#/ACC BYTE# VI/O 26 Notes: 1. WP#/ACC has internal pull up. 2. VI/O voltage must tight with VCC for MX68GL1G0F H/L. |
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