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AD7472ARZ Datasheet(PDF) 10 Page - Analog Devices |
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AD7472ARZ Datasheet(HTML) 10 Page - Analog Devices |
10 / 20 page REV. B AD7470/AD7472 –10– CIRCUIT DESCRIPTION CONVERTER OPERATION The AD7470/AD7472 are 10-bit/12-bit successive approxima- tion analog-to-digital converters based around a capacitive DAC. The AD7470/AD7472 can convert analog input signals in the range 0 V to VREF. Figure 2 shows a very simplified sche- matic of the ADC. The control logic, SAR, and the capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. CAPACITIVE DAC SWITCHES SAR CONTROL LOGIC COMPARATOR OUTPUT DATA 10-/12-BIT PARALLEL VIN VREF CONTROL INPUTS Figure 2. Simplified Block Diagram of AD7470/AD7472 Figure 3 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on VIN. COMPARATOR VIN CONTROL LOGIC CAPACITIVE DAC AGND 2k SW2 SW1 A B Figure 3. ADC Acquisition Phase Figure 4 shows the ADC during conversion. When conversion starts, SW2 will open and SW1 will move to position B, causing the comparator to become unbalanced. The ADC then runs through its successive approximation routine and brings the comparator back into a balanced condition. When the compara- tor is rebalanced, the conversion result is available in the SAR register. COMPARATOR VIN CONTROL LOGIC CAPACITIVE DAC AGND 2k SW2 SW1 A B Figure 4. ADC Conversion Phase TYPICAL CONNECTION DIAGRAM Figure 5 shows a typical connection diagram for the AD7470/ AD7472. Conversion is initiated by a falling edge on CONVST. Once CONVST goes low, the BUSY signal goes high, and at the end of conversion, the falling edge of BUSY is used to acti- vate an interrupt service routine. The CS and RD lines are then activated in parallel to read the 10- or 12-data bits. The recom- mended REF IN voltage is 2.5 V providing an analog input range of 0 V to 2.5 V, making the AD7470/AD7472 a unipolar ADC. It is recommended to perform a dummy conversion after power-up as the first conversion result could be incorrect. This also ensures that the part is in the correct mode of operation. The CONVST pin should not be floating when power is applied as a rising edge on CONVST might not wake up the part. In Figure 5 the VDRIVE pin is tied to DVDD, which results in logic output voltage values being either 0 V or DVDD. The voltage applied to VDRIVE controls the voltage value of the output logic signals. For example, if DVDD is supplied by a 5 V supply and VDRIVE by a 3 V supply, the logic output voltage levels would be either 0 V or 3 V. This feature allows the AD7470/AD7472 to interface to 3 V parts while still enabling the ADC to process signals at 5 V supply. 10 F 0.1 F PARALLED INTERFACE 2.5V* *RECOMMENDED REF IN VOLTAGE 0V TO REF IN 1nF 10 F 0.1 F 47 F AD7470/ AD7472 AVDD VDRIVE DVDD REF IN DB0– DB9 (DB11) CS BUSY CONVST RD VIN C/ P ANALOG SUPPLY 2.7V–5.25V ++ Figure 5. Typical Connection Diagram |
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