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ADUM1510BRWZ Datasheet(PDF) 8 Page - Analog Devices |
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ADUM1510BRWZ Datasheet(HTML) 8 Page - Analog Devices |
8 / 12 page ADuM1510 Data Sheet Rev. B | Page 8 of 12 APPLICATIONS INFORMATION PCB LAYOUT The ADuM1510 digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 9). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VDD2. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin must not exceed 10 mm. Bypass- ing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless the ground pair on each package side is connected close to the package. VDD1 GND1 VIA VIB VIC VID VIE GND1 VDD2 GND2 VOA VOB VOC VOD VOE GND2 ADuM1510 Figure 9. Recommended PCB Layout See the AN-1109 Application Note for board layout guidelines. PROPAGATION DELAY-RELATED PARAMETERS Propagation delay is a parameter that describes the length of time it takes for a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to a logic high output. INPUT (VIx) OUTPUT (VOx) tPLH tPHL 50% 50% Figure 10. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved. Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuM1510 component. Propagation delay skew refers to the maximum amount that the propagation delay differs among multiple ADuM1510 components operated under the same conditions. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable and is, therefore, either set or reset by the pulses indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no pulses for more than approximately 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a default low state by the watchdog timer circuit (see Table 8). The limitation on the magnetic field immunity of the device is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The analysis below defines such conditions. In the follow- ing analysis, the ADuM1510 is examined in a 3 V operating condition because it represents the most susceptible mode of operation of all products in its product family. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold of approximately 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ/dt) Σπrn2; n = 1, 2, … N where: β is the magnetic flux density (gauss). rn is the radius of the nth turn in the receiving coil (cm). N is the number of turns in the receiving coil. Given the geometry of the receiving coil in the ADuM1510 and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field can be calculated, as shown in Figure 11. MAGNETIC FIELD FREQUENCY (Hz) 100 0.001 1M 10 0.01 1k 10k 10M 0.1 1 100M 100k Figure 11. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maxi- mum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This voltage is approximately 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), the received pulse is reduced from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. |
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