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ADSP-2163BP-66 Datasheet(PDF) 5 Page - Analog Devices |
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ADSP-2163BP-66 Datasheet(HTML) 5 Page - Analog Devices |
5 / 64 page ADSP-21xx REV. B –5– Figure 1. ADSP-21xx Block Diagram One bus grant execution mode (GO Mode) allows the ADSP- 21xx to continue running from internal memory. A second execution mode requires the processor to halt while buses are granted. Each ADSP-21xx processor can respond to several different interrupts. There can be up to three external interrupts, configured as edge- or level-sensitive. Internal interrupts can be generated by the timer, serial ports, and, on the ADSP-2111, the host interface port. There is also a master RESET signal. Booting circuitry provides for loading on-chip program memory automatically from byte-wide external memory. After reset, three wait states are automatically generated. This allows, for example, a 60 ns ADSP-2101 to use a 200 ns EPROM as external boot memory. Multiple programs can be selected and loaded from the EPROM with no additional hardware. The data receive and transmit pins on SPORT1 (Serial Port 1) can be alternatively configured as a general-purpose input flag and output flag. You can use these pins for event signalling to and from an external device. The ADSP-2111 has three additional flag outputs whose states are controlled through software. A programmable interval timer can generate periodic interrupts. A 16-bit count register (TCOUNT) is decremented every n cycles, where n–1 is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). Serial Ports The ADSP-21xx processors include two synchronous serial ports (“SPORTs”) for serial communications and multiproces- sor communication. All of the ADSP-21xx processors have two serial ports (SPORT0, SPORT1) except for the ADSP-2105, which has only SPORT1. The serial ports provide a complete synchronous serial interface with optional companding in hardware. A wide variety of framed or frameless data transmit and receive modes of opera- tion are available. Each SPORT can generate an internal programmable serial clock or accept an external serial clock. Each serial port has a 5-pin interface consisting of the following signals: Signal Name Function SCLK Serial Clock (I/O) RFS Receive Frame Synchronization (I/O) TFS Transmit Frame Synchronization (I/O) DR Serial Data Receive DT Serial Data Transmit The ADSP-21xx serial ports offer the following capabilities: Bidirectional—Each SPORT has a separate, double-buffered transmit and receive function. Flexible Clocking—Each SPORT can use an external serial clock or generate its own clock internally. R Bus 16 DMD BUS HOST PORT CONTROL PMD BUS DMA BUS PMA BUS 14 24 16 EXTERNAL ADDRESS BUS EXTERNAL DATA BUS HOST PORT DATA BOOT ADDRESS GENERATOR TIMER 14 11 BUS EXCHANGE COMPANDING CIRCUITRY 5 16 24 RECEIVE REG TRANSMIT REG SERIAL PORT 1 EXTERNAL HOST PORT BUS DMA BUS PMA BUS DMD BUS PMD BUS HOST INTERFACE PORT (ADSP-2111 Only) FLAGS (ADSP-2111 Only) 3 PROGRAM SEQUENCER INSTRUCTION REGISTER PROGRAM MEMORY SRAM or ROM DATA MEMORY SRAM DATA ADDRESS GENERATOR #2 DATA ADDRESS GENERATOR #1 14 INPUT REGS OUTPUT REGS SHIFTER INPUT REGS OUTPUT REGS MAC INPUT REGS OUTPUT REGS ALU RECEIVE REG TRANSMIT REG SERIAL PORT 0 (Not on ADSP-2105) 5 16 MUX 24 MUX |
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