FEDL610Q411-02

LAPIS Semiconductor

ML610Q411/ML610Q412/ML610Q415

10/36

ML610Q412 Chip Pin Layout & Dimension

SEG21

91

SEG22

92

SEG23

93

SEG24

94

SEG25

95

SEG26

96

47 VSS

SEG27

97

46 VDD

SEG28

98

45 VSS

SEG29

99

44 P03

SEG30 100

43 P02

SEG31 101

42 P01

SEG32 102

41 P00

SEG33 103

40 NMI

SEG34 104

39 P11

SEG35 105

38 P10

SEG43 106

37 (NC)

SEG42 107

36 AIN1

SEG41 108

35 AIN0

SEG40 109

SEG39 110

SEG38 111

SEG37 112

SEG36 113

*

2.836mm

2.636mm

* Dummy pad

Note: These dummy pads are visible and do have any function, they are placed for a mechanical evaluation

in LAPIS Semiconductor. Please do NOT implement wire-bonding to the dummy pad.

Chip size:

2.836mm x 2.636mm

PAD count:

95 pins

Minimum PAD pitch:

80

m

PAD aperture:

70

m  70 m

Chip thickness:

350

m

Figure 6 ML610Q412 Chip Layout & Dimension