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MLX83203 Datasheet(PDF) 8 Page - Melexis Microelectronic Systems |
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MLX83203 Datasheet(HTML) 8 Page - Melexis Microelectronic Systems |
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8 / 35 page  MLX83202/MLX83203 Automotive NFET pre-drivers 3901083203 Page 8 of 35 Prelim. Data Sheet Rev 2.2 4 Dec 2013 P.54 Programmable Vds monitor blanking time: Internal delay between GATE signal high and enabling the corresponding Vds monitor Tvds_bl VDS_BLANK_TIME[1:0] =00 01 10 11 0.59 1.22 2.5 4.9 0.75 1.5 3 6 0.93 1.94 4.12 8.44 us P.56 Sleep gate discharge resistor Rsgd Internal resistance between FET gate-source pins to switch-off FET. VDD = 0V (sleep mode) VGS =0.5V 1 KOhm P.57 Trickle charge pump current capability Itcp VSUP>12V, PHASE2/3 = VSUP, CP2/3=PHASE2/3+6.5V -35 -25 uA P.58 VGS undervoltage high Vgs_UVH ICOM released 42 70 %VREG VGS undervoltage low Vgs_UVL Warning on ICOM 36 63 %VREG P.60 PWM frequency F_dr_pwm 5 20 100 KHz P.61 Leakage from CPx to PHx Rcp_leak Typ at room temperature Min at 150C Tj 0.75 1 MOhm Logic IO (FET inputs, EN input) P.63 Digital input high Voltage VIN_dig_h Minimum voltage for input to be treated as logical high 70 %VDD P.64 Digital input low Voltage VIN_dig_l Maximum voltage for input to be treated as logical low 30 %VDD P.65 Input pull-up resistance RIN_dig_pu FETB1, FETB2, FETB3 90 410 KOhm P.66 Input pull-down resistance RIN_dig_pd FETT1,FETT2, FETT3 90 410 KOhm P.67 Input pull-down resistance R_EN_pd EN 90 410 KOhm SPI timing P.68 SPI initial setup time Tspi_isu 2 us P.69 SPI clock frequency Fspi 500 KHz P.70 Rise/fall times Tspi_rf CLK, CSB, MISO, MOSI 200 ns P.71 CSB setup time TCSB_su 1 us P.72 CSB high time TCSB_H 2 us P.73 Clock high time TCLK_H 1 us P.74 Clock low time TCLK_L 1 us P.75 Data in setup time TDI_su 1 us P.76 Data in hold time TDI_h 500 us P.77 Data out ready delay TDO_r Cload at FETB1<50pF 500 us EEPROM read delay T_EE_RD EE_RD = 1 6 us EEPROM write delay T_EE_WR EE_RD = 1 12 ms ICOM output P.78 pullup current ICOM_PU Vicom=0V -2.23 -5 mA P.79 pulldown current ICOM_PD Vicom=VDD 5 2.6 mA Enable input P.80 Bridge disable propagation delay EN_PR_DEL From Bridge enable EN < 0.2*VDD to VGS < 0.5V, Cload=1nF 1 us |
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