HEF4015BT datasheet(6/15 Pages) NXP

Part #	HEF4015BT

Description	Tolerant of slow clock rise and fall times

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HEF4015B

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Product data sheet

Rev. 8 — 21 November 2011

6 of 15

NXP Semiconductors

HEF4015B

Dual 4-bit static shift register

11. Dynamic characteristics

[1]

The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

Table 7.

Dynamic characteristics

VSS = 0 V; CL = 50 pF; Tamb = 25 C.

Symbol

Parameter

Conditions

VDD

Extrapolation formula[1] Min

Typ

Max

Unit

tPHL

HIGH to LOW

propagation delay

nCP to Qn;

see Figure 4

5 V

103 ns + (0.55 ns/pF)CL

-

130

260

ns

10 V

44 ns + (0.23 ns/pF)CL

-

55

110

ns

15 V

32 ns + (0.16 ns/pF)CL

-

4080ns

nMR to Qn;

see Figure 6

5 V

78 ns + (0.55 ns/pF)CL

-

105

210

ns

10 V

34 ns + (0.23 ns/pF)CL

-

4590ns

15 V

27 ns + (0.16 ns/pF)CL

-

3570ns

tPLH

LOW to HIGH

propagation delay

nCP to Qn

see Figure 4

5 V

93 ns + (0.55 ns/pF)CL

-

120

240

ns

10 V

44 ns + (0.23 ns/pF)CL

-

55

110

ns

15 V

32 ns + (0.16 ns/pF)CL

-

4080ns

tt

transition time

see Figure 4

5 V

10 ns + (1.00 ns/pF)CL

-60

120

ns

10 V

9 ns + (0.42 ns/pF)CL

-

3060ns

15 V

6 ns + (0.28 ns/pF)CL

-

2040ns

tsu

set-up time

nD to nCP;

see Figure 5

5 V

+25

15

-

ns

10 V

+25

10

-

ns

15 V

+20

5-

ns

th

hold time

nD to nCP;

see Figure 5

5 V

40

20

-

ns

10 V

20

10

-

ns

15 V

15

8

-

ns

tW

pulse width

nCP LOW;

minimum width;

see Figure 5

5 V

60

30

-

ns

10 V

30

15

-

ns

15 V

20

10

-

ns

nMR HIGH;

minimum width;

see Figure 6

5 V

80

40

-

ns

10 V

30

15

-

ns

15 V

24

12

-

ns

trec

recovery time

pin nMR;

see Figure 6

5 V

50

20

-

ns

10 V

30

10

-

ns

15 V

20

5

-

ns

fmax

maximum frequency

see Figure 5

5 V

7

15

-

MHz

10 V

15

30

-

MHz

15 V

22

44

-

MHz

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