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HEF4049BT Datasheet(PDF) 2 Page - NXP Semiconductors |
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HEF4049BT Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 12 page HEF4049B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 — 18 November 2011 2 of 12 NXP Semiconductors HEF4049B Hex inverting buffers 5. Functional diagram 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 1. Logic symbol Fig 2. Logic diagram for one gate Fig 3. Input protection circuit 001aai331 3 1A 1Y 2 5 2A 2Y 4 7 3A 3Y 6 9 4A 4Y 10 11 5A 5Y 12 14 6A 6Y 15 mna341 A Y 001aae604 input VSS Fig 4. Pin configuration HEF4049B VDD n.c. 1Y 6Y 1A 6A 2Y n.c. 2A 5Y 3Y 5A 3A 4Y VSS 4A 001aae602 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 Table 2. Pin description Symbol Pin Description VDD 1 supply voltage 1Y to 6Y 2, 4, 6, 10, 12, 15 output |
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