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R5F564MJDDLC Datasheet(PDF) 7 Page - Renesas Technology Corp |
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R5F564MJDDLC Datasheet(HTML) 7 Page - Renesas Technology Corp |
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7 / 67 page  RX64M Group 1. Overview Under development Preliminary document Specifications in this document are tentative and subject to change. R01DS0173EJ0090 Rev.0.90 Page 7 of 67 Feb 28, 2014 Communication function Ethernet controller (ETHERC) 2 channels Input and output of Ethernet/IEEE 802.3 frames Transfer at 10 or 100 Mbps Full- and half-duplex modes MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as defined in IEEE 802.3u Detection of Magic PacketsTM*1 or output of a "wake-on-LAN" signal (WOL) Compliance with flow control as defined in IEEE 802.3x standards Filtering of multicast frames Direct transfer of frames between two channels by cut-through PTP controller for Ethernet controller (PTP) A block compatible with the IEEE 1588 standard is connected to the Ethernet controller (ETHERC). Matching with a time stamp can start counting by MTU3 and the GPT. DMA controller for Ethernet controller (EDMAC) 3 channels (the round-robin method determines the priority of the channels) 2 channels for ETHERC; 1 channel for EPTPC Alleviation of CPU load by the descriptor control method Transmission FIFO: 2 Kbytes; Reception FIFO: 4 Kbytes USB 2.0 FS host/ function module (USBb) Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS One port Compliance with the USB 2.0 specification Transfer rate: Full speed (12 Mbps) Self-power mode and bus power are selectable OTG (On the Go) operation is possible Incorporates 2 Kbytes of RAM as a transfer buffer External pull-up and pull-down resistors are not required USB 2.0 FS host/ function module with battery charging (USBA) Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS One port (only in 176-pin devices) Compliance with the USB 2.0 specification Transfer rate: full speed (12 Mbps), low speed (1.5 Mbps) (host only) Self-power mode and bus power are selectable OTG (On the Go) operation is possible Incorporates 8.5 Kbytes of RAM as a transfer buffer External pull-up and pull-down resistors are not required Serial communications interfaces (SCIg, SCIh) 9 channels (SCIg: 8 channels + SCIh: 1 channel) SCIg Serial communications modes: Asynchronous, clock synchronous, and smart-card interface Multi-processor function On-chip baud rate generator allows selection of the desired bit rate Choice of LSB-first or MSB-first transfer Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12 Start-bit detection: Level or edge detection is selectable. Simple I2C Simple SPI 9-bit transfer mode Bit rate modulation Double-speed mode Event linking by the ELC (only on chanel 5) SCIh (The following functions are added to SCIg) Supports the serial communications protocol, which contains the start frame and information frame Supports the LIN format Serial communications interface with FIFO (SCIFA) 4 channels Methods of transfer: Asynchronous and clock synchronous Desired bit rates can be selected from the internal baud rate generators. LSB or MSB first is selectable. Both the transmission and reception sections are equipped with 16-byte FIFO buffers, allowing continuous transmission and reception. Bit rate modulation Double-speed mode Table 1.1 Outline of Specifications (6/9) Classification Module/Function Description |
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