RENESAS TECHNICAL UPDATE TN-RX*-A086A/E

Date: Jan. 30, 2014

Page 11 of 16

Page 191

Correct a description in ‘Table 6.1 List of I/O Registers (Address Order) (56/56)’.

ICLK > PCLK

ICLK < PCLK

000C30AEh

DPC

Overvoltage Output

Error Judgment

Threshold Setting

Register 3

ERRVTH3

16

16

3 to 5 PCLKA

2, 3 ICLK

1638

Not present in

versions with

64 or 48 pins.

000C30B2h

DPC

PWM Shut-Down at

Overvoltage Output

Error Setting Register

ERRDWN

16

16

3 to 5 PCLKA

2, 3 ICLK

1638

Not present in

versions with

64 or 48 pins.

DPC

Address

Module

Symbol

Register Name

Register

Symbol

Remarks

Number

of bits

Access

size

Number of Access States

Module

Name

Reference

Page

Page 525

Correct a description in ‘Table 21.6 Register Settings for Input/Output Pin Function in 144-Pin LQFP’.

PSEL[4:0]Settings

Pin

P10

P11

P12

P13

P14

00000b (initial value)

Hi-Z

00010b

MTCLKD

MTCLKC

—

—

—

01010b

—

—

—

CTS2# RTS2#

SS2#

SCK2

10001b

—

—

USB0_DPRPD USB0_VBUSEN —

Page 525

Correct a description in ‘Table 21.9 Register Settings for Input/Output Pin Function in 64-Pin LQFP’.

PSEL[3:0] Settings

Pin

P10

P11

0000b (initial value)

Hi-Z

0010b

MTCLKD

MTCLKC