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NI 5751 CLIP Node IO Descriptions

Port Name

Type

Function

ADC Error

A

Boolean When ADC Error A is asserted the width of the sampling window from ADC A has shrunk below its required value, which does not guarantee that the

data can be sampled correctly. This could be caused by a noisy clock source, a damaged ADC, or an incompatible NI FlexRIO FPGA module. ADC

Error A is a sticky bit and is cleared upon reinitialization. 3

ADC Error

B

Boolean When ADC Error B is asserted the width of the sampling window from ADC B has shrunk below its required value, which does not guarantee that the

data can be sampled correctly. This could be caused by a noisy clock source, a damaged ADC, or an incompatible NI FlexRIO FPGA module. ADC

Error B is a sticky bit and is cleared upon reinitialization. 3

PLL

Unlocked

Boolean Indicates that the PLL has become unlocked since the board was initialized. When the PLL is unlocked IO Mod Clock 0 is disabled. When set, PLL

Unlocked is cleared upon reinitialization.

This signal should be inside a single-cycle timed loop with a clock source of the 40 MHz onboard clock.

3

SPI Idle 4

Boolean Indicates the SPI engine is idle and ready for a SPI read or write transaction. This signal should be inside a single-cycle timed loop with a clock source

of the 40 MHz onboard clock.

SPI Device

Select 4

U8

Selects which ADC the SPI port will communicate with. This signal should be inside a single-cycle timed loop with a clock source of the 40 MHz onboard

clock.

SPI

Address 4

U8

The address of the register in the ADC selected. This signal should be inside a single-cycle timed loop with a clock source of the 40 MHz onboard clock.

SPI Write

Data 4

U16

Data to be written to the register in the ADC selected. This signal should be inside a single-cycle timed loop with a clock source of the 40 MHz onboard

clock.

SPI Write 4

Boolean Begin SPI write transaction. The SPI Write signal should be inside a single-cycle timed loop with a clock source of the 40 MHz onboard clock.

Initialization

During initialization, the CLIP does the following:

Resets a PLL in the CLIP that is used to receive data from the ADCs.

Resets the deserialization circuit.

Recalibrates the data delays for capturing the data using dynamic phase alignment.

Aligns the two ADC ICs to each other.

Clears ADC Error

.

X

Manual Initialization

The user FPGA code must manually start initialization in the following instance:

When using DStarA or CLK IN as the ADC sample clock and the frequency of the clock has changed since the last initialization.

To manually start initialization, the user FPGA code must assert Force Initialization.

Note When initialization starts, the Initialization Done signal deasserts within 100 ns. Initialization Done does not assert again until initialization has completed. You can

expect a delay of up to 2 seconds before Initialization Done asserts again, depending on your clock rate. If you read the Initialization Done indicator before it has had

time to deassert (100 ns), you may get a false positive.

Automatic Initialization

The CLIP performs initialization automatically in the following instances:

The FPGA IO is enabled to the NI 5751

The user FPGA code changes the Sample Clock Select signal

FPGA IO is enabled automatically when the CLIP is loaded into the FPGA. You can also programmatically enable and disable the FPGA IO from the host VI. When FPGA IO is

enabled, the CLIP resets all ADC registers.

Caution Do

execute user FPGA code using IO Module Clock 0 until Initialization Done is True. While Initialization Done is False, the clocks are not stable.

not

If the user FPGA code changes the Sample Clock Select signal, the CLIP begins initialization automatically; you do not need to assert Force Initialization.

Note When initialization starts, the Initialization Done signal deasserts within 100 ns. Initialization Done does not assert again until initialization has completed. You can

expect a delay of up to 2 seconds before Initialization Done asserts again, depending on your clock rate. If you read the Initialization Done indicator before it has had

time to deassert (100 ns), you may get a false positive.

Accessing SPI Registers

The ADC register maps are included in the AD9252 datasheet. The following application note found on Analog Devices' Web site contains more information and SPI functionality

for the AD9252: AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

SPI reads from the AD9252 are not supported on the NI 5751. The SPI access does not actually take effect until the software transfer bit (bit 0) of the device_update (offset

register is written.

0xFF)

To access a register in an ADC, complete the following steps: