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SEP04G72G1AH2MT-25R Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers |
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SEP04G72G1AH2MT-25R Datasheet(HTML) 8 Page - List of Unclassifed Manufacturers |
8 / 16 page Data Sheet Rev.1.2 14.02.2014 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 8 CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 16 Parameter & Test Condition Symbol max. Unit 6400-CL6 5300-CL5 OPERATING WRITE CURRENT: All device banks open, Continuous burst writes; One module rank active; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle IDD4W 2376 2196 mA BURST REFRESH CURRENT: tCK = tCK (IDD); refresh command at every tRFC (IDD) interval, CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle IDD5 2736 2646 mA SELF REFRESH CURRENT: CK and CK# at 0V; CKE ≤ 0.2V; All other Control and Address bus inputs are floating at VREF; DQ’s are floating at VREF IDD6 252 252 mA OPERATING CURRENT*) : Four device bank interleaving READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are not changing during DESELECT; DQ inputs changing once per clock cycle IDD7 3906 3456 mA *) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. TIMING VALUES USED FOR IDD MEASUREMENT IDD MEASUREMENT CONDITIONS SYMBOL 6400-CL6 5300-CL5 Unit CL (IDD) 6 5 tCK tRCD (IDD) 15 15 ns tRC (IDD) 60 60 ns tRRD (IDD) 7.5 7.5 ns tCK (IDD) 2.5 3.0 ns tRAS MIN (IDD) 45 45 ns tRAS MAX (IDD) 70’000 70’000 ns tRP (IDD) 15 15 ns tRFC (IDD) 127.5 127.5 ns |
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