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SEU01G72D4BH1MT-37R Datasheet(PDF) 1 Page - List of Unclassifed Manufacturers

Part # SEU01G72D4BH1MT-37R
Description  1GB ECC DDR2 . SDRAM DIMM
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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SEU01G72D4BH1MT-37R Datasheet(HTML) 1 Page - List of Unclassifed Manufacturers

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Data Sheet
Rev.1.1
03.01.2013
Swissbit AG
Industriestrasse 4
Fon: +41 (0) 71 913 0303
www.swissbit.com
Page 1
CH-9552 Bronschhofen
Fax: +41 (0) 71 913 0315
eMail: info@swissbit.com
of 16
1GB ECC DDR2 – SDRAM DIMM
240 Pin ECC UDIMM
SEU01G72D4BH1MT-XXR
1GByte in FBGA Technology
RoHS compliant
*) The refresh rate has to be doubled when 85°C<TC<95°C
Environmental Requirements:
Operating temperature (ambient)
standard Grade
0°C to 70°C
Grade W
-40°C to 85°C
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Options:
Data Rate / Latency
Marking
DDR2 667 MT/s CL5
-30
DDR2 533 MT/s CL4
-37
Module Density
1024MB with 9 dies and 1 rank
Standard Grade
(TC)
0°C to 85°C
(TA)
0°C to 70°C
Grade W
(Tc)
-40°C to 95°C
(TA)
-40°C to 85°C
Features:
240-pin 72-bit DDR2 Dual-In-Line Double Data Rate
Synchronous DRAM Module with ECC support
Module organization: single rank 128M x 72
VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V
1.8V I/O ( SSTL_18 compatible)
Serial Presence Detect (SPD) EEPROM
Gold-contact pad
This module is fully pin and functional compatible to the
JEDEC PC2-6400 spec. and JEDEC- Standard MO-237.
(see www.jedec.org)
The pcb and all components are manufactured according
to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR2 - SDRAM component Micron
MT47H128M8CF-25 DIE-Rev.H
128Mx8 DDR2 SDRAM in FBGA-60 package
Four bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Eight internal device banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency
– 1 tCK
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
Figure: mechanical dimensions
1
1if no tolerances specified ± 0.15mm


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