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OPA4830IPW Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # OPA4830IPW
Description  Quad, Low-Power, Single-Supply, Wideband Operational Amplifier
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

OPA4830IPW Datasheet(HTML) 3 Page - National Semiconductor (TI)

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ELECTRICAL CHARACTERISTICS: VS = ±5V
OPA4830
www.ti.com.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
Boldface limits are tested at +25
°C.
At TA = +25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted.
OPA4830IPW
TYP
MIN/MAX OVER TEMPERATURE
0
°C to
–40
°C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
°C
+25
°C(2)
+70
°C(3)
+85
°C(3)
UNITS
MAX
LEVEL
(1)
AC PERFORMANCE (see Figure 74)
Small-Signal Bandwidth
G = +1, VO ≤ 0.2VPP
280
MHz
typ
C
G = +2, VO ≤ 0.2VPP
120
66
64
61
MHz
min
B
G = +5, VO ≤ 0.2VPP
23
16
14
13
MHz
min
B
G = +10, VO ≤ 0.2VPP
11
8
7
6
MHz
min
B
Gain-Bandwidth Product
G
≥ +10
110
80
77
75
MHz
min
B
Peaking at a Gain of +1
VO ≤ 0.2VPP
6
dB
typ
C
Slew Rate
G = +2, 2V Step
560
275
265
255
V/
µs
min
B
Rise Time
0.5V Step
3.4
5.9
5.95
6.0
ns
max
B
Fall Time
0.5V Step
3.6
6.0
6.05
6.1
ns
max
B
Settling Time to 0.1%
G = +2, 1V Step
43
64
66
67
ns
max
B
Harmonic Distortion
VO = 2VPP, f = 5MHz
2nd-Harmonic
RL = 150Ω
–60
–53
–51
–50
dBc
max
B
RL ≥ 500Ω
–68
–58
–57
–56
dBc
max
B
3rd-Harmonic
RL = 150Ω
–59
–50
–49
–48
dBc
max
B
RL ≥ 500Ω
–77
–65
–62
–55
dBc
max
B
Input Voltage Noise
f > 1MHz
9.5
10.6
11.1
11.6
nV/
√Hz
max
B
Input Current Noise
f > 1MHz
3.7
4.8
5.3
5.8
pA/
√Hz
max
B
NTSC Differential Gain
0.07
%
typ
C
NTSC Differential Phase
0.17
°
typ
C
DC PERFORMANCE
(4)
RL = 150Ω
Open-Loop Voltage Gain
74
66
65
64
dB
min
A
Input Offset Voltage
±2
±8
±9.4
±9.8
mV
max
A
Average Offset Voltage Drift
±30
±30
µV/°C
max
B
Input Bias Current
VCM = 0V
+5
+10
+12
+13
µA
max
A
Input Bias Current Drift
±44
±46
nA/
°C
max
B
Input Offset Current
VCM = 0V
±0.2
±1.1
±1.3
±1.5
µA
max
A
Input Offset Current Drift
±5
±5
nA/
°C
max
B
INPUT
Negative Input Voltage
(5)
–5.5
–5.4
–5.3
–5.2
V
max
A
Positive Input Voltage
(5)
3.2
3.1
3.0
2.9
V
min
A
Common-Mode Rejection Ratio (CMRR)
Input-Referred
80
76
74
71
dB
min
A
Input Impedance
Differential Mode
10 || 2.1
k
Ω || pF
typ
C
Common-Mode
400 || 1.2
k
Ω || pF
typ
C
OUTPUT
Output Voltage Swing
G = +2, RL = 1kΩ to GND
±4.88
±4.86
±4.85
±4.84
V
min
A
G = +2, RL = 150Ω to GND
±4.64
±4.60
±4.58
±4.56
V
min
A
Current Output, Sinking and Sourcing
±82
±63
±58
±53
mA
min
A
Short-Circuit Current
Output Shorted to Ground
±150
mA
typ
C
Closed-Loop Output Impedance
G = +2, f
≤ 100kHz
0.06
typ
C
(1)
Test levels: (A) 100% tested at +25
°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
(2)
Junction temperature = ambient for +25
°C specifications.
(3)
Junction temperature = ambient at low temperature limits; junction temperature = ambient +19
°C at high temperature limit for over
temperature specifications.
(4)
Current is considered positive out of pin.
(5)
Tested < 3dB below minimum specified CMRR at ± CMIR limits.
Copyright © 2006–2008, Texas Instruments Incorporated
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