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THS4215DGN Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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THS4215DGN Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 50 page THS4211 THS4215 SLOS400E – SEPTEMBER 2002 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted). (1) UNIT Supply voltage, VS 16.5 V Input voltage, VI ±VS Output current, IO 250 mA Continuous power dissipation See Dissipation Ratings Table Maximum junction temperature, TJ (2) +150°C Maximum junction temperature, continuous operation, long-term reliability TJ (3) +125°C Storage temperature range, Tstg –65°C to +150°C HBM 4000 V ESD ratings CDM 1500 V MM 200 V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. PACKAGE DISSIPATION RATINGS (1) POWER RATING (3) θJC θJA (2) PACKAGE (°C/W) (°C/W) TA≤ +25°C TA= +85°C D (8-pin) 38.3 97.5 1.02 W 410 mW DGN (8-pin)(1) 4.7 58.4 1.71 W 685 mW DGK (8-pin) 54.2 260 385 mW 154 mW DRB (8-pin) 5 45.8 2.18 W 873 mW (1) The THS4211/5 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heat sink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the PowerPAD thermally enhanced package. (2) This data was taken using the JEDEC standard High-K test PCB. (3) Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and long term reliability. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT Dual supply ±2.5 ±7.5 Supply voltage, (VS+ and VS–) V Single supply 5 15 Input common-mode voltage range VS– + 1.2 VS+ – 1.2 V 2 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated Product Folder Link(s): THS4211 THS4215 |
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