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THS4524MDBTEP Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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THS4524MDBTEP Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 48 page THS4524-EP www.ti.com SBOS609A – JUNE 2012 – REVISED AUGUST 2013 ELECTRICAL CHARACTERISTICS: VS+ – VS– = 3.3 V (continued) At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RL = 1 kΩ differential, G = 1 V/V, single-ended input, differential output, and input and output referenced to midsupply, unless otherwise noted. TA = -55°C to 125°C TEST PARAMETER CONDITIONS MIN TYP MAX UNIT LEVEL(1) Two-tone, f1 = 2 MHz, f2 = 2.2 MHz, Third-Order Intermodulation Distortion –90 dBc C VOUT = 2-VPP envelope Input Voltage Noise f > 10 kHz 4.6 nV/ √Hz C Input Current Noise f > 100 kHz 0.6 pA/ √Hz C Overdrive Recovery Time Overdrive = ±0.5 V 80 ns C Output Balance Error VOUT = 100 mV, f ≤ 2 MHz (differential input) –57 dB C Closed-Loop Output Impedance f = 1 MHz (differential) 0.3 Ω C Channel-to-Channel Crosstalk f = 10 kHz, measured differentially –125 dB C DC PERFORMANCE Open-Loop Voltage Gain (AOL) 80 116 dB A Input-Referred Offset Voltage ±0.5 ±7 mV A Input offset voltage drift(3) ±2 μV/°C C Input Bias Current 0.75 3.8 μA A Input bias current drift(3) ±1.75 nA/°C C Input Offset Current ±0.03 ±2.0 uA A Input offset current drift(3) ±0.1 nA/°C C (3) Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at –55°C and +125°C, computing the difference, and dividing by 180. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links :THS4524-EP |
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