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EP4CGX150 Datasheet(PDF) 4 Page - Altera Corporation

Part # EP4CGX150
Description  1. Cyclone IV FPGA Device Family Overview
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP4CGX150 Datasheet(HTML) 4 Page - Altera Corporation

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Chapter 1: Cyclone IV FPGA Device Family Overview
Device Resources
Cyclone IV Device Handbook,
February 2013
Altera Corporation
Volume 1
Table 1–2 lists Cyclone IV GX device resources.
Table 1–2. Resources for the Cyclone IV GX Device Family
Resources
Logic elements (LEs)
14,400
21,280
29,440
29,440
49,888
73,920
109,424
149,760
Embedded memory (Kbits)
540
756
1,080
1,080
2,502
4,158
5,490
6,480
Embedded 18 × 18 multipliers
0
40
80
80
140
198
280
360
General purpose PLLs
1
2
2
4 (4)
4 (4)
4 (4)
4 (4)
4 (4)
Multipurpose PLLs
2 (5)
2 (5)
2 (5)
2 (5)
4 (5)
4 (5)
4 (5)
4 (5)
Global clock networks
20
20
20
30
30
30
30
30
High-speed transceivers (6)
244488
8
8
Transceiver maximum data rate
(Gbps)
2.5
2.5
2.5
3.125
3.125
3.125
3.125
3.125
PCIe (PIPE) hard IP blocks
111111
1
1
User I/O banks
9 (7)
9 (7)
9 (7)
11 (8)
11 (8)
11 (8)
11 (8)
11 (8)
Maximum user I/O (9)
72
150
150
290
310
310
475
475
Notes to Table 1–2:
(1) Applicable for the F169 and F324 packages.
(2) Applicable for the F484 package.
(3) Only two multipurpose PLLs for F484 package.
(4) Two of the general purpose PLLs are able to support transceiver clocking. For more information, refer to the Clock Networks and PLLs in
Cyclone IV Devices chapter.
(5) You can use the multipurpose PLLs for general purpose clocking when they are not used to clock the transceivers. For more information, refer
to the Clock Networks and PLLs in Cyclone IV Devices chapter.
(6) If PCIe
1, you can use the remaining transceivers in a quad for other protocols at the same or different data rates.
(7) Including one configuration I/O bank and two dedicated clock input I/O banks for HSSI reference clock input.
(8) Including one configuration I/O bank and four dedicated clock input I/O banks for HSSI reference clock input.
(9) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver
pins and dedicated configuration pins are not included in the pin count.


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