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CS52843EDR8 Datasheet(PDF) 5 Page - Cherry Semiconductor Corporation |
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CS52843EDR8 Datasheet(HTML) 5 Page - Cherry Semiconductor Corporation |
5 / 6 page When the power supply sees a sudden large output cur- rent increase, the control voltage will increase allowing the duty cycle to momentarily increase. Since the duty cycle tends to exceed the maximum allowed to prevent trans- former saturation in some power supplies, the internal oscillator waveform provides the maximum duty cycle clamp as programmed by the selection of oscillator timing components. Figure 2: Timing Diagram Figure 3: Oscillator Timing Network and Parameters Setting the Oscillator The times Tc and Td can be determined as follows: tc = RTCT ln td = RTCT ln Substituting in typical values for the parameters in the above formulas: VREF = 5.0V, VUPPER = 2.7V, VLOWER = 1.0V, Id = 8.3mA, then tc ≈ 0.5534RTCT td = RTCT ln For better accuracy RT should be ≥10kΩ. Grounding High peak currents associated with capacitive loads neces- sitate careful grounding techniques. Timing and bypass capacitors should be connected close to Gnd in a single point ground. The transistor and 5kΩ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Sense. ) 2.3 - 0.0083 RT 4.0 - 0.0083 RT ( ) VREF - IdRT - VLOWER VREF - IdRT - VUPPER ( ) VREF - VLOWER VREF - VUPPER ( VCC IO VO Switch Current EA Output Toggle F/F Output OSC RESET VOSC 5 Circuit Description VREF OSC Gnd RT CT Vupper Vlower tc td VOSC Internal Clock LARGE RT (≈10kΩ) VREF Internal Clock SMALL RT (≈700kΩ) Triangular Mode Sawtooth Mode |
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