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CDB4228 Datasheet(PDF) 7 Page - Cirrus Logic |
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CDB4228 Datasheet(HTML) 7 Page - Cirrus Logic |
7 / 30 page CS4228 DS307PP1 7 SWITCHING CHARACTERISTICS (Continued) Notes: 8. After powering up the CS4228, RST should be held low until the power supplies and clocks are settled. Parameter Symbol Typ Max Units RST Low Time (Note 8) 1- - ms SCLK Falling Edge to SDOUT Output Valid (DSCK=0) tdpd -TBD ns LRCK Edge to MSB Valid tlrpd -TBD ns SDIN Setup Time Before SCLK Rising Edge tds -TBD ns SDIN Hold Time After SCLK Rising Edge tdh -TBD ns Master Mode SCLK Falling to LRCK Edge tmslr +10 - ns SCLK Duty Cycle 50 - % Slave Mode SCLK Period tsckw -- ns SCLK High Time tsckh TBD - - ns SCLK Low Time tsckl TBD - - ns SCLK rising to LRCK Edge (DSCK=0) tlrckd TBD - - ns LRCK Edge to SCLK Rising (DSCK=0) tlrcks TBD - - ns Figure 1. Serial Audio Port Master Mode Timing t mslr SCLK* (output) LRCK (output) SDOUT sckh sckl sckw t t t MSB MSB-1 *SCLK shown for DSCK = 0. SCLK inverted for DSCK = 1. tdpd SDOUT LRCK (input) SCLK* (input) SDIN1 SDIN2 SDIN3 dh t ds t lrpd t lrcks t lrckd t Figure 2. Serial Audio Port Slave Mode Timing |
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Similar Description - CDB4228 |
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